Debug for SoCs adds new requirements and challenges in terms of adding visibility and control to a system, simplifying integration of hardware and software instrumentation into design flows, and supporting emerging needs for architectures incorporating complex network on chip buses, multiple cores, multithreading, embedded security, power management and other issues. The OCP-IP Debug Working Group addresses the definition of debug resources and integration to enable comprehensive debug of OCP based systems. Contributors include OCP-IP companies (IP venders, systems integrators, end customers) addressing the need for debug solutions and/or debug of the OCP Infrastructure.

The initial focus is on definition of debug signals at the OCP Socket and fabric levels, but leaves their specific implementation open to IP and tools venders. The scope does not address in detail the external debug interfaces between an OCP Debug Interface Socket with on-chip Debug environment and external components (probes, debuggers, etc). These pin level interfaces are considered separate from the OCP Debug System and are being addressed by other industry working groups (Nexus, MIPI, IJTAG, Multicore Association Debug Working Group, etc). The OCP Debug Infrastructure defines requirements for interfaces between the Debug and EDA infrastructure and features, but does not address specific debug to EDA interfaces, which are again specific to different implementations.

Access the entire document on the OCP International Partnership (OCP-IP) website.