July 9, 2007 -- As power has become more expensive in electronic systems, the need to specify low power design intent has increased in importance. Whereas dynamic power (aka, switching) is fairly well handled using existing design and verification tools and methods, management of static power consumption (aka, leakage) requires the use of new design techniques that fall outside the capabilities of existing HDLs. If HDLs cannot capture the low power design intent, then verification tools can neither simulate nor prove that the low power design intent is correct. Also, implementation tools require proprietary mechanisms so that users can provide the necessary information to create the low power chip.
The EDA industry responded with various ways to augment logic design with low power formats. However, the lack of a single, standard format resulted in costly inefficiencies and an error-prone process resulting form the need to rewrite the low power specification for each tool in the design and verification flow, severely impacting productivity, profit margin, and design quality.
For this reason, Accellera, at the request and assistance of end users and with technical donations and contributions from multiple EDA vendors, developed the Unified Power Format (UPF) to capture low power design intent in a portable and interoperable form that can be used with most design verification and implementation tools throughout the design flow.
By Stephen Bailey. (Bailey is Product Marketing Manager at Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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Mentor Graphics Corp.