September 11, 2007 -- It is no longer a mystery for designers and manufacturers of 45-nm chips that higher process variability negatively impacts design performance, predictability and parametric yield. Manufacturing and process variations result in physical changes in devices and interconnect leading to deviations in their electrical behavior. Essentially, "what you design is not what you get" in the manufactured silicon and this manifests itself as electrical variability.

What good is it to migrate to a smaller geometry if the advantages of doing so, in terms of die size, performance, power and predictability, are lost due to increased design margins or parametric yield loss? This article outlines an end-to-end flow from parametric characterization, modeling to design analysis, optimization and final signoff. It offers a methodology for 45-nm design that minimizes the impact of potential systematic (lithography, chemical mechanical planarization) and random variations.

By Prashant Maniar, Amit Majumdar, Hitendra Divecha, Michael Jacobs, and Rahul Deokar. (Maniar is co-founder and chief strategy officer, Majumdar is vice president of engineering and architect, and Divecha is the Director of Marketing and Applications, all with Stratosphere Solutions, Inc.; Jacobs and Deokar are with Cadence Design Systems, Inc.)