SOCcentral: How to Enhance Signal Integrity in High-Density FPGA-based Designs (EE Times Embedded 23783)

You are at: The item(s) you requested.

Friday, May 24, 2013

How to Enhance Signal Integrity in High-Density FPGA-based Designs Featured

Publication: EE Times Embedded
Contributor: Ittiam Systems, Ltd.

Printer friendly

E-Mail Item URL

September 13, 2007 -- Platform verification boards typically have multiple FPGAs and hundreds of signals that are either terminated or non-terminated running between them. Checking the connectivity and locating fabrication and assembly faults becomes a must before the actual bitstream is loaded on the FPGAs for verification.

By Rajendra Turakani and Ritesh Ramesh Parekh. (Turakani is Senior Engineer and Parekh is lead engineer for multimedia systems at Ittiam Systems, Ltd.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times Embedded website.

Read more about
Ittiam Systems, Ltd.
on SOCcentral.com

Keywords: Ittiam Systems, EE Times Embedded, signal integrity, PCB design, FPGAs, field programmable gate arrays, verification,

579/23783 9/13/2007 7574 480

Designer's Mall

0.15625

Search site for:
Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification

Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP

Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!

Mike Donlin
The Write Solution
Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL

Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search
SOC Design ASIC Design ASIC Verification FPGA Design CPLD Design PCB Design DSP Design RTOS Development Digital Design	Analog Design Mixed-Signal Design DFT DFM IC Packaging VHDL Verilog SystemC SystemVerilog