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JTAG Guidelines for Board DFT: Part 2  
Company: ASSET InterTech, Inc.
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This document is Part 2 of a 2-part document that contains a series of design-for-testability (DFT) Guidelines for printed circuit boards (PCBs) to be tested primarily through the use of boundary scan techniques that are based on the IEEE 1149.1-2001 Standard.

Access the entire document on the ASSET InterTech, Inc. website.

E-mail ASSET InterTech, Inc. for more information.

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ASSET InterTech, Inc.
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Keywords: ASSET InterTech, PCB design, JTAG, boundary scan, design for test, design-for-test, DFT, EDA tools,
205/23858 10/3/2007 8344 453
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