October 19, 2007 -- Power closure has moved to the forefront of design challenges for today’s chip projects. Leakage power increases with each new process generation. Smaller geometries enable designs to fit more functions into less space, running at a higher speed. This situation creates exponential growth in power density, presenting a heat-removal challenge for all types of design, especially high-speed applications whose power you’ve never had to worry about before.
As if meeting aggressive frequencies and managing power consumption were not big enough challenges on their own, frequency and power are actually opposing forces. In other words, optimizing for speed causes an increase in power, and, conversely, techniques to reduce power reduce speed.
This effect most often manifests itself during physical implementation, when long wires make timing closure more challenging. At this point, timing optimization generally involves upsizing; using low-voltage-threshold, high-leakage-power cells; buffer insertion; and other techniques that increase power. It is generally too late in the design cycle to make changes to the RTL structure or the power architecture or to use techniques such as multiple-supply voltage or power shut-off. Such modifications would require you to repeat functional verification, not to mention another spin through implementation. As a result, logic designers feel helpless, left to hope that power consumption won’t require a different package, the removal of functions, or other drastic measures that would cause the project to miss its market window. Figure 1 illustrates a typical power-unpredictability scenario. As tapeout nears, the designer must decide whether to sacrifice costs and, for example, add an expensive cooling mechanism or sacrifice the schedule to rebuild.
The root cause of the problem is that few designers effectively enough measure power in the process when they can take action. The logic designer’s lament is “If I had only known earlier, I could have done something about it.” What can you do to improve power predictability?
By Jack Erickson. (Erickson is a product-marketing director at Cadence Design Systems, Inc. where he is responsible for the Encounter RTL Compiler synthesis and Cadence Logic Design Team Solutions.)
This brief introduction has been excerpted from the original copyrighted article.
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