| Processor Core Power Specs: A Cautionary Tale | Company: Tensilica, Inc.
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Anyone familiar with board-level design has developed an intuitive feel for packaged-processor power specifications: the processor draws a certain amount of power, give or take a percentage based on process variation and speed binning. For a variety of reasons, this intuition utterly fails with respect to vendor specifications for processor core IP.
While a packaged processor’s measured power specs must necessarily account for all circuitry in the package, processor core power specifications are based on simulations—vendors are free to delete or ignore any number of power-dissipating functions when reporting power numbers. Many factors will greatly affect the power specifications listed on the processor core’s spec sheet, including the target fabrication technology (both the lithography size and the process), the cell library used to generate the core, and the execution activity imposed on the processor during power simulation. Consequently, caution and judicious reading of the vendor data sheets are called for when comparing the power numbers for competing processor IP. Rarely will you find apples to compare to apples from the data sheets alone.
Access the entire document on the Tensilica, Inc. website.
| E-mail Tensilica, Inc. for more information.
Read more about Tensilica, Inc. on SOCcentral.com |
| Keywords: Tensilica, FPGAs, field programmable gate arrays, IP, intellectual property, cores, microprocessors, MPUs, ASIC design,
| | 205/24414 11/23/2007 6227 389 | Add a comment or evaluation (anonymous postings will be deleted)
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