December 4, 2007 -- There are have been numerous papers written on the techniques that can be employed during integrated circuit (IC) design to achieve better overall manufacturability and yield. These design-for-manufacturing (DFM) techniques have historically been grouped by the yield limiting affects that they are meant to mitigate, such as wire spreading for particulate (or random) based yield loss, influence rules for systematic (or lithography) based yield loss and metal density control for parametric yield.
While these DFM techniques were useful, they lacked a strategy for easy deployment and acceptance by the design community. Many times, the designers were expected to understand complex relationships between different yield limiters and even if they did understand, the industry was slow to provide sufficient fab data to allow the designers to make the necessary trade-offs. When data became available the bigger problem became that there was no automation in place to help designers implement the trade-offs. Because of this much of what has been espoused as DFM had been relegated to the design of smaller IP blocks where designers could manually handle the required trade-offs.
In an effort to realize a more wide spread use of DFM techniques, Microsoft, Pyxis, PDF and Ponte conducted an experiment to establish a methodology for proactively using DFM techniques during the routing phase of the design flow and create a strategy for quantifying the performance and yield impacts of that methodology.
By PT Patel, Mitchell Heins, Surbhi Agarwal, Doug Stiles, Simon Favre, and Carlo Guardiani. (Patel, Heins, and Agarwal are with Pyxis Technology Inc.; Stiles is with Microsoft Corp.; Simon Favre is with Ponte Solutions; and Guardiani is with PDF Solutions, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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Pyxis Technology, Inc.