December 3, 2007 -- The efficient design of complex, multimedia-intensive, heterogeneous multiprocessing (HMP) system-on-chips (SoCs) for inclusion in HDTVs and related consumer-oriented systems presents a daunting array of challenges. A collaborative effort among IC designers using CoWare's ESL tools and Sonics' SMX smart-interconnect IP designed for this class of SoCs enabled the rapid optimization and verification of the design aspects necessary to meet the critical architectural challenges.
Home-entertainment-enamored consumers and the press celebrate the convergence of communications, multimedia, high-definition video with high-quality multichannel audio, widely adopted technical standards and the resultant, rapidly declining prices that enable mass production and proliferation of these mini-miracles. However, with design cycles under extreme pressure from concept to tapeout, and demanding IDMs being forced to change specifications and features late in the design cycle as standards evolve or competition motivates additional capabilities or price points, what is to be done?
Most commonly, difficulties with timing closure are frequently encountered, necessitating tedious critical-path analyses and modifications to the logic, often requiring re-simulation and re-verification efforts before final tapeout. However, with the existence of a robust, high-level model, these efforts may be greatly simplified.
By Tom De Schutter and Jeff Haight. (De Schutter is marketing manager for IP models and third-party relationships at CoWare, Inc., and Haight is director of technical marketing at Sonics, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Engineering Times (EE Times) website.
Read more about