December 21, 2007 -- CMOS technology enables a single FPGA device to have many I/O interfaces. Recently, low power has emerged as a principal theme in high-speed I/O interfaces, and voltage reduction offers the most effective means of minimizing power consumption. As a result, the noise margin of these I/O interfaces has become smaller. Thus, it is essential for FPGA users to quantify system-level simultaneous switching noise (SSN) in a chip/package/PCB environment. This article offers a systematic SSN overview with the focus on SSN caused by FPGA output buffers.
This noise is widely known as simultaneous switching output noise (SSO), and is differentiated from the SSN caused by input buffers. A description of the causes of system-level SSO is presented, and a hierarchical system-level SSO modeling methodology is proposed. A procedure for correlating the SSO models to frequency- and time-domain measurements is provided and several PCB design methodologies for minimizing SSO in PCBs are offered.
An FPGA-mounted PCB is a complex system that can be divided into the die, which contains active circuits; the package, which supports routing with embedded passives; and the board, which provides the connection between the FPGA and the outside world. It is difficult to characterize noises inside the chip for this type of system.
Thus, it is valuable to quantify SSO at either near- or far-ends of PCB traces connected to the FPGA. Two primary factors contribute to SSO: power distribution network (PDN) impedance and mutual inductive coupling among switching I/Os.
By Geing Liu, Hong Shi, Alan Chang, and Sam Wong. (Liu is Technical Staff Member, Characterization Group, Product Engineering; Shi is Manager, Packaging Design Engineering; Chang is Senior Product Engineer; and San Wong is Senior Manager, Product Engineering, at Altera Corp.)
This brief introduction has been excerpted from the original copyrighted article.
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