February 21, 2008 -- The history of the EDA industry shows a clear, repetitive pattern. Designers develop new proprietary technologies, leveraging de facto and sanctioned industry standards; leading-edge users identify the most effective of these new technologies; and the industry turns the knowledge that users gain into the next set of de facto or sanctioned standards, allowing the creation of a set of newer technologies.
From the first netlist languages to Verilog to SystemVerilog, the functional verification of the digital-design segment of the EDA industry has seen—and continues to see—a rich sequence of ever-more-powerful standards. The methodology and associated support classes that the VMM (Verification Methodology Manual) for SystemVerilog describes were the next logical steps in this constant industrial evolution. Arising from proprietary methodologies that Synopsys and ARM developed, VMM has become a de facto standard for implementing constrained random-verification environments in SystemVerilog.
A standard verification methodology enables the industry evolution to continue to the next level of productivity. Just as VMM’s creators built it on SystemVerilog, you can now build application packages on the infrastructure that the VMM provides. User testbenches can then leverage the functions that those application packages provide, making them easier to implement correctly and increasing efficiency.
By Janick Bergeron. (Bergeron is with Synopsys, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.
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