Page loading . . .

  
 You are at: The item(s) you requested.Friday, May 24, 2013
Multi-language Functional Verification Coverage for Multi-site Projects   Featured
Publication: EE Times EDA Designline
Contributor: Cadence Design Systems, Inc.
 Printer friendly
 E-Mail Item URL

February 18, 2008 -- Today's design paradigm is changing rapidly, or to be more accurate, it has already dramatically changed! Time to market pressures imply that most of today's SOC designs are re-use based derivative designs. This paradigm shift has created entirely new challenges for both design and verification teams, especially in the case of large projects that are developed throughout multiple sites. A significant part of the design cycle now involves managing and automating much of the SOC level integration that comes from the various sites. In order to address these issues we must first recognize the following:
  • IP blocks that form a part of the SoC could come from multiple sources spread over multiple geographies.
  • Different IP blocks may be written in various languages, making the SoC a multi-language design.
  • Each IP block carries its own verification IP so the overall verification environment may also be multi-language and distributed.

All this poses significant challenges for the overall verification effort. SOC integration teams must first ensure that they can verify the entire SOC in a timely manner, and ensure the highest quality of verification.

By Apurva Kalia. (Kalia is Vice President of R&D for Incisive Simulation Products at Cadence Design Systems, Inc.)

This is Part 1 of a two parts article.

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Cadence Design Systems, Inc.
on SOCcentral.com

Keywords: EE Times EDA Designline, cadence Design Systems, IP, intellectual property, cores, functional verification, ASIC design, EDA tools,
580/25144 2/18/2008 9093 357


Designer's Mall
0.1601563



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.25