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Physically Aware Test Development  
Publication: EE Times EDA Designline
Contributor: Magma Design Automation, Inc.
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February 5, 2008 -- As designs move to smaller nanometer processes, test development is becoming more difficult, effectively impeding product release. Not only are test sets growing at a very high rate, but they are unable to provide adequate levels of coverage that older metrics such as static, stuck-at fault coverage used as a measure. Now, the actual value and quality of a set of test vectors depends upon many other factors. One of the first signs that more test types were required appeared when early adopters of the 130-nm processes also were early movers towards timing-based testing. They had to make the transition due to the number of test escapes they were seeing compared to the earlier processes. As the industry moves to smaller feature sizes, even more complicated tests will become necessary.

In the latest semiconductor processes, relative test quality is dropping due in part to increasing design complexity, decreasing feature sizes, uncompromising performance requirements, and the increasing interactions between design and layout. Low-quality testing results in a number of problems concerning the definition of good or not-good parts and batches of parts that fall into one of the following anomalies:devices "work" some of the time; devices pass on the tester, but fail in systems; devices work in systems, but fail on the tester; and devices pass structural test, but fail functional test.

Therefore, manufacturers and designers are forced to look at new test techniques to get better correlation between the test and final applications. These new test techniques, which typically use physical design information to handle complex defect mechanisms, are the result of experience with the processes and research into the various failure mechanisms from both industry and academia.

By Geir Eide. (Eide is Senior Product Manager at Magma Design Automation, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Magma Design Automation, Inc.
on SOCcentral.com

Keywords: EE Times EDA Designline, Magma Design Automation, design for test, design-for-test, DFT, test generation, ASIC design, EDA tools,
580/25145 2/5/2008 7392 384


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