February 11, 2008 -- To build increasingly sophisticated chips, engineers must be freed from low-level details and limiting methodologies. ESL design flows raise the level of abstraction from the register transfer level (RTL) to the system level. For today's multimedia and wireless devices, this is mandatory and is in fact analogous to the transition the industry made from schematics to RTL over 15 years ago. By working at the system level, design teams increase flexibility, improve verification and reduce design time. ESL delivers these benefits by enabling advanced methodologies based on second-generation, system-level tools and languages.
ESL methodologies are already in use in production design flows today. Many of the consumer electronic products sold during the last holiday season (such as HDTVs and wireless mobile devices) contained semiconductors built using ESL methods. A typical ESL design flow starts with untimed C code to model the system and develop algorithms. The high-speed models allow for extensive verification at the system level. The untimed C code is then refined for hardware implementation using C synthesis, which automatically generates the RTL implementation. Formal equivalence checking is used throughout the process to keep C code refinements in sync with the original untimed model and to comprehensively verify that the RTL functionality matches the C code.
But tools alone are not sufficient. Just as hardware engineers know how to write RTL to get predictable gate-level results, experienced ESL designers know how to write system-level code that yields high-quality RTL. Hardware designers moving to ESL will find that many of the best RTL design practices are not the same with ESL. For those who don't understand these nuances, there can be considerable pain. However, those who do will realize vast improvements in their daily design and verification tasks.
Experienced designers write the initial C code so that much of it can be reused in later refinements. This requires an understanding of how to express hardware detail in C code while maintaining fast simulations. By using algorithmic data types that faithfully represent hardware semantics such as truncation, rounding and overflow, the chance of introducing errors during refinement is reduced and simulation performance maintained. When C code is written that adheres to the ever-growing synthesizable subset, less refinement for synthesis is needed, leaving more time to focus on system performance and RTL quality-of-results (QoR).
The best way to demonstrate the power of ESL is to look at some real-world examples of complete ESL flows and ways in which designers are successfully raising the level of semiconductor design. Below are two case studies of ESL methodologies deployed at leading semiconductor companies in existing projects; the first uses an ESL virtual prototype and the other an FPGA prototype.
By Bryan Bowyer and Mitch Dale. (Dale is Director of Product Marketing at Calypto Design Systems, inc. and Bowyer is a Technical Marketing Engineer in Mentor Graphics Corp.'s High-level Synthesis Division.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Engineering Times (EE Times) website.
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Calypto Design Systems, Inc.