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Interfacing High-Performance 32-bit Cores to MCU-based Memory Architectures  
Publication: EE Times Embedded
Contributor: MIPS Technologies, Inc.
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April 10, 2008 -- As higher-performance 32-bit processor cores begin to make large gains into the microcontroller (MCU) space currently dominated by 8- and 16-bit devices, chip architects are facing similar challenges in system design that PC designers faced about a decade ago. While the speed and performance of the new cores has increased, some of the key supporting technologies have not kept up, resulting in severe performance bottlenecks.

Most microcontrollers rely completely on internal memory devices of two types. Moderate amounts of SRAM provide the required data storage space, and NOR FLASH provides the instruction and constant data space.

Embedded SRAM technology is keeping pace with the increase in both size and operation speed of the new 32-bit cores. Mature SRAM technology is easily available in the 10ns (100 MHz) operational range and is cost-effective at this speed grade for the typical RAM sizes required by microcontrollers.

But standard NOR FLASH is lagging behind the basic 32-bit core clock speed by almost an order of magnitude. Current embedded NOR FLASH technology is sitting at around 50ns (20MHz) access times. This introduces a real bottleneck in the ability to transfer data between the FLASH device and the core, since the core can waste several clock cycles waiting for the specific instruction to be retrieved by the FLASH memory.

By Bob Martin. (Martin is a Senior Applications Engineer for MIPS Technologies, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Embedded website.

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Keywords: EE Times Embedded, MIPS Technologies, microcontrollers, MCUs, IP, intellectual property, cores,
580/25536 4/10/2008 2771 348


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