May 12, 2008 -- During the past three decades, the mainstream design entry for semiconductor-design has steadily evolved from layout, to transistors, to gates, and, most recently, to the register-transfer level (RTL). Each time the complexity at one level became unmanageable, four crucial steps were required to enable the shift to the next higher level.
For example, during the shift to RTL in the 1990s, these steps included: 1) abstraction from gates to RTL available in several proprietary languages, 2) RTL finding its use for analysis and verification, 3) availability of an automated path from RTL back to gates and 4) the introduction of equivalence checking between RTL and gate-level to ensure that the automated implementation path actually worked correctly.
Arguably, all these steps occurred somewhat independently, but they certainly became mainstream when the RTL and automated implementation (using Verilog and a synthesizable subset) worked hand-in-hand.
For the next shift ó to electronic system-level (ESL) design &mdash the same four steps are required, and again, standardization is the key enabler for the transition to mainstream adoption. Beyond signal-level RTL is the transaction level. The primary users for simulation and analysis at the SystemC transaction level are software developers starting pre-silicon development long before RTL is verified and available. Strong links to verification already exist, however, across all major simulation solutions with mixed-language (SystemVerilog/ VHDL/ SystemC) simulation offerings. Although a synthesizable subset for SystemC is under development, it's somewhat distant from mainstream use at this point. Similarly, the first commercial solutions for equivalence checking between transaction-level SystemC and RTL are on the horizon but are in their early stages. So, while not all four steps have yet entered mainstream adoption, their mere presence and the analogy with the shift from gate-level to RTL make ESLís eventual adoption appear inevitable.
The key driver for ESL and its adoption by software developers with virtual platforms is the new reality of the relationship between hardware- and software-development efforts. At 90nm, the typical overall chip-related development effort for software has already surpassed the effort for hardware, and this trend will only escalate. By 2011, market-research firm International Business Strategies, Inc. projects that less than 40% of the overall development effort for 45-nm designs will be spent on hardware.
Standardization will drive the adoption of virtual platforms
To date, lack of standardization has inhibited widespread adoption of virtual platforms. Over the past decade, proprietary solutions for virtual platforms designed to accelerate early software development have been introduced by several companies, including AXYS Design Automation (now ARM), CoWare, VaST, Virtio (now Synopsys) and Virtutech. These virtual platforms had to include several key technology components to enable the fast simulation speeds expected by programmers. In the absence of standards, these platforms were originally implemented using proprietary technology components. One could argue that the inaugural era of virtual platforms has come to an end, given that the first set of customers have been served for whom the pressure to enable pre-silicon embedded software development was great enough that they were willing to live with proprietary solutions.
Today, the industry is ready to enter the era of virtual platform interoperability enabled by standardization. The continuing shift to increased effort spent on software has caused sufficient user pressure to drive virtual platform-related standardization as part of the Open SystemC Initiative (OSCI), now enabling SystemC-based virtual platforms that are fast enough for early software development and verification. The new SystemC TLM-2 specification includes the transaction abstractions so that all virtual platform components can communicate and be interoperable. The draft standard has passed public review and is on track to be ratified mid-year 2008 and subsequently contributed to IEEE. At the most recent North American SystemC User Group meeting, TLM-2 early adopters reported processor-based platforms running at 250MIPS utilizing SystemC TLM-2.
The magnitude of this standardization is equivalent to the introduction of Verilog in the late 1980s ó leading to the eventual demise of proprietary languages like HiLo, DABL, UDL/I and N-dot. SystemC TLM-2 is the key enabler for a standards-based virtual platform ecosystem with model interoperability and is the key enabler for virtual platform adoption.
But we have to walk before we can run! The first major ESL application ready to enter mainstream is the next generation of virtual platforms for pre-silicon software development enabled by SystemC TLM-2.0 standardization. Once full interoperability for the main use model of early software development on virtual platforms has been achieved, the other steps of links to verification, the automated path to implementation and subsequent equivalence will follow naturally, making the shift to ESL complete.
By Frank Schirrmeister.
As Director, Product Management at Synopsys, Inc., Frank is responsible for the System-Level Solutions products Innovator, DesignWare System-Level Library and System Studio with a focus on virtual platforms for early software development. Prior to joining Synopsys, Frank held senior management positions at Imperas, ChipVision, Cadence, AXYS Design Automation and SICAN Microelectronics. Most recently he served as Vice President of marketing at Imperas, a provider of solutions for multicore software development. At Cadence, he served as Group Director of Verification Marketing in the Design and Verification Business Unit.
Go to the Synopsys, Inc. website to learn more.