May 17, 2008 -- As the complexity of designs has scaled, the need to provide accurate physical constraints like timing, area, power and port locations has become very important. Of these, timing constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the total effort to achieve timing closure, but also reduce the number of iterations to achieve that goal.
These constraints undergo several refinements as they are pushed through the design flow from RTL to post layout. This requires that constraints be managed at each step and properly handed off to the next step to ensure that design intent is preserved. If constraints are not managed properly, unnecessary iterations between front-end and back-end groups occur, and time to market and end unit cost is impacted.
The landscape becomes more complicated when handoff has to happen between tools from different vendors. This results in the need to manage constraints in different formats. The challenge is to check that these constraints model the same timing behavior and produce the same timing results irrespective of the format that has been used to specify them. The goal of the designer is simple " to carefully monitor the changes in his timing constraints throughout the design flow and check at each step that constraints from the previous step are in sync with the current step. With different ways to model the same timing behavior, the designer needs to manage these constraints to ensure faster timing closure and reduced iterations to make design schedules more predictable.
By Sridhar Gangadharan and Ramesh Dewangan. (Gangadharan is the Product Director of Timing Constraints and RTL Analysis with Atrenta, Inc. and Dewangan is Product Marketing Director with Atrenta.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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