May 14, 2008 -- With the advent of advanced HDLs, such as SystemVerilog, that provide new and powerful language constructs, current hardware modeling styles can now be enhanced both in terms of abstraction level and overall efficiency. Developing concise, accurate designs entails learning how SystemVerilog features can be effectively used to design efficient and synthesizable models for both ASICs and FPGAs. This article will focus on the impact of new extensions and constructs in SystemVerilog on hardware designs and describe the usefulness and compatibility of these constructs vis-à-vis pure Verilog constructs.
As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog: 1) enhance conciseness and expressiveness of designs, 2) add built-in checks to avoid design issues, 3) design efficient FSM and RAM/ROM memory models, and 4) graduate to object oriented generic hardware designs.
In Part 1 we examined Steps1 and 2 – conciseness of expression and built-in code verification. Now, in Part 2, we will elaborate on Steps 3 and 4 and demonstrate how designers can improve code encapsulation, re-use, and consistency in model behavior – all without adversely affecting the quality of results.
By Sachin Kakkar, Sanjay Gupta, Ayan Banerjee, and Rohit Goel. (Kakkar, Gupta, Banerjee, and Goel are all with Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Programmable Logic Designline website.
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