July 22, 2008 -- As power efficiency technology moves into a new generation, it has become more sophisticated--depending more and more on interaction between ICs. The next generation of power efficiency technology will require a heavy dose of institutional knowledge integration. A holistic, system-level view of power management and ever-advancing chip technologies is becoming increasingly important, heightening the need for open conversations and collaboration between DSP, SOC, MCU and analog power management designers. Additionally, semiconductor companies must find ways for system designers to take advantage of the sophisticated techniques built into the chips. Otherwise, all of the potential energy savings cannot be wrung out of a system.
From a system-design perspective components need to work together at a very high level of sophistication, and this begins while the SOC or DSP is still being designed. Analog, MCU and power supply designers can provide invaluable input to the SOC or DSP design team.
As product features grow and consumer expectations rise, the imperative to do more with less never changes. Semiconductor technology is playing a key role in energy conservation by combining efficiency and intelligence. Building efficiency into the chips and system designs that go into products we use daily helps take some of the burden off the consumer.
The migration from 90-nm to 65-nm to 45-nm process nodes has produced lower-power chips in large part because higher-density chips run at lower voltages —and power scales as a square of voltage. There are tradeoffs, however, because the thinner isolation layers of advanced processes allow greater leakage current when a particular circuit is quiescent.
By Leon Adams, Kevin Belnap and Jeff Falin. (Adams is the DSP Strategic Marketing Manager for Texas Instruments, Inc. Belnap is Product Marketing Manager for TI's MSP430 ultralow-power microcontroller group, and Falin is a factory applications engineer with TI's high-performance analog, portable power applications group.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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