September 2, 2008 -- The viability of the semiconductor IC industry is based on a continued decrease in the average cost per transistor. The largest factors affecting transistor costs moving forward relate to semiconductor yield. Both the attainable volume yield level, as well as the time to achieve this level (time-to-yield), have significant effects on the cost of a semiconductor product. There is growing acceptance that performance related issues such as signal integrity and cross talk are becoming the dominant factor affecting yield.

Unfortunately, performance issues are often not well understood and are becoming more complex with each new process technology. Indeed with tighter processes and increasingly complex designs, subtle defects and process-design interactions are resulting in an exploding number of different performance issues. Because of the design-specific nature of these performance issues, it is no longer sufficient to simply improve the process technology or create process-specific design rules to address yield. Adaptive solutions that can analyze and correct design specific yield issues are needed.

Since yield levels are becoming design-dependent, it is now becoming important to not only improve the yield level for each new design but to do so in an acceptable amount of time. Exacerbating this time-to-yield issue is that increasingly, an acceptable yield level can only be achieved through a design re-spin in order to correct design specific issues. A design re-spin typically adds anywhere between 4 to 8 months to the design phase. This can have a very large impact on profitability due to additional engineering costs and more importantly, due to market share loss resulting from time-to-market delays. Clearly, yield enhancement solutions that can avoid design re-spins will be important moving forward. At the very least, solutions that can improve diagnostics in order to speed time to a necessary re-spin are needed.

Despite up-front yield-related design improvements, deep nanometer designs are going to continue to experience performance related yield issues that will only be discovered once silicon is available. How quickly and accurately these performance issues are measured will determine how quickly and effectively they can be corrected. This of course will have a direct impact on yield levels and yield ramp time. The first requirement for effective yield improvement is the availability of detailed and accurate data that profiles the capabilities and performance of the semiconductor part at both the pin and sub-die levels.

A technology that is gaining wide acceptance for effective failure and performance diagnosis is built-in self-test (BIST). BIST is a natural evolution of two distinct test approaches: External ATE and conventional design-for-test (DFT). Building on conventional DFT approaches such as scan, BIST integrates the high-speed and high-bandwidth portions of the external ATE directly into the ICs. BIST consists of user-configurable IP, in the form of design objects generally delivered as RTL soft cores. These IP design objects implement pattern generators (either random or algorithmic), results compression, and precision timing for at-speed delivery of the tests. BIST controllers (engines) can be created for the test and measurement of virtually all components of an SOC: logic, memories, high speed I/Os and mixed-signal circuits. As depicted in Figure 1, controllers are typically distributed throughout the design using a highly scalable hierarchical communication infrastructure based on the IEEE 1149.1 and 1500 standards, making communication simple and efficient.

Figure 1: Comprehensive BIST Infrastructure.

Although BIST has historically been used for achieving high-quality test and reducing test costs, it's highly distributed nature makes it very effective at detecting and diagnosing failures and performance issues deep within the die. For example, with logic BIST, each design flip-flop becomes a virtual performance monitor as each captures the results of thousands of at-speed test patterns. In today's large designs, this provides literally millions of monitors throughout the die. Even parametric measurements can be made. For example, a commercial SerDes BIST solution provides measurement of key SerDes I/O parameters such as jitter and jitter tolerance with sub-picosecond accuracy.

The detailed diagnostic data obtained from the various BIST resources can generally be extracted and data-logged with little to no extra test time in a full production environment. Results obtained across multiple wafers can be analyzed to detect and characterize systematic issues effecting performance and yield. Depending on the nature of the issue, information can be sent back directly to design engineering to perform corrective actions to the design or the diagnostic information can be fed to failure analysis teams in order to perform more root cause analysis. In both cases, BIST provides a key component in quickly finding and correcting yield limiting issues.

By Stephen Pateras.

Pateras is Senior Director Strategic Technology at LogicVision, Inc.