Page loading . . .

  
 You are at: The item(s) you requested.Friday, April 18, 2014
A Comprehensive Approach to Manufacturing Variability   Featured
Contributor: Mentor Graphics Corp.
 Printer friendly
 E-Mail Item URL

September 2, 2008 -- A growing challenge for IC designers at advanced process nodes is controlling manufacturing variability during the design. Variability in manufacturing is emerging as a leading cause for chip failures and delayed schedules, with growing consequences for the bottom-line. In addition, companies are ramping to new technology nodes faster and are having difficulty keeping up with the proliferation of new design rules, which means more expensive late-cycle respins and the danger of missing narrow market windows.

Manufacturing variability that leads to yield loss is not just the fab's problem; silicon debug is only a diagnostic. Even waiting until the physical verification stage to make DFM corrections is too late because some high-impact yield enhancements are too disruptive late in the design cycle, and can ruin timing, signal integrity (SI), performance, or other constraints. The lack of integration between place-and-route, verification, and test makes it difficult to be confident that your design is "litho/manufacturing-friendly" and will yield as expected. The traditional flow, in which the design is "tossed over the wall" at each design stage and DFM information flows in only one direction, is ultimately a failing strategy (see Figure 1). The best methodology for designing highly manufacturable ICs starts in place-and-route using sign-off DFM metrics, and continues through DFM verification, mask preparation, test, and yield diagnosis.

Figure 1. In the one-directional flow of DFM information, the traditional approach misses opportunities to improve manufacturability earlier in the design cycle. Each step needs to be more tightly integrated within a complete DFM flow.


Without a complete design flow in place to control the variability inherent in advanced ICs, teams typically apply excessive guardbanding, such as adding extra margin to timing and power constraints. From a competitive viewpoint, this is over-constraining the design rules. They might be forced to eliminate certain physical features, even though it means giving up some of the advantages of using advanced process nodes. The value of DFM/DFY tools lies not only in achieving higher yield, but in faster time-to-market and higher product performance. At 45nm and below, manufacturing variability has turned DFM from an optional methodology to a required component of the design flow. Luckily, there are powerful new DFM tool flows available now. Companies that invest will gain the application experience needed to handle full production, and to incorporate their use into processes before they face yield-limiting situations or missed market windows.

Trends towards DFM/DFY

Several trends are aligning to make DFM a requirement in the physical design and verification flow. First is the limitation of 193-nm visible light lithography, which cannot draw 45-nm or smaller features without distortion in the manufactured shapes of devices and interconnects relative to ideal physical dimensions. Such distortions can lead to catastrophic chip failures due to bridging and pinching, and also to out-of-spec chips that do not perform as expected. Traditionally, we could simply use optical proximity correction (OPC) techniques after tape out to correct these distortions, but today's design need additional design constraints to eliminate physical features that increase the probability of defects. Further, to accurately determine which features will be problematic, we need to use complex two- and three-dimensional modeling that accounts for electrical interactions and "as-built" polygon contours (shapes rounded and distorted by the litho process).

Design rules for advanced processes look more like mathematical equations than simple linear measurement thresholds. Besides being more computationally intensive, this "equation-based DRC" depends on close calibration to a specific manufacturing process. Therefore, the value of advanced physical verification tools depends on whether they have been compared with real silicon test chips, a procedure called "silicon validation." This calibration must be performed with each distinct manufacturing process recipe and fabrication line.

A second trend is that the performance of devices and interconnects have become much more sensitive to small variations in the rendered shapes. Much of the variability comes from the lithographic process window mentioned above; for example, variations in exposure and focus can alter the dimensions and contours of "printed" features. However, other effects also contribute to variability, such as deviations in planarity due to chemical metal polishing (CMP) limitations, and proximity effects that depend on how devices and interconnects are placed with respect to each other and may not be accounted for in cell library models. These proximity effects operate not only within a single layer (2D effects), but also between one or more layers of the design (3D effects). These variations can affect device parameters such as transistor slew rate, drive capability and leakage as well as interconnect parasitics, including resistance, capacitance and, for RF circuits, inductance. To ensure a robust design, physical design and verification must support design rules that reflect these complex relationships. In addition, timing closure has to consider many design corners that reflect the extremes of these interacting variables.

In addition to variability from manufacturing processes (corners), more design variability is introduced by the proliferation of operational modes. For example, to maximize battery life and reduce temperature hot spots and heat dissipation, new designs commonly have multiple operational modes, such as standby, sleep, and active. Devices often need to run at different combinations of supply voltage and clock frequencies. These considerations are added to the traditional environmental variations, such as ambient temperature and voltage supply tolerances. Closing a design for timing, power, SI, area, and manufacturing across all corners and modes adds a whole new meaning to complexity for designers.

Third, with design rules becoming so numerous, complex and subtle, the signoff decision itself is evolving, from a relatively straightforward pass-fail proposition to an assessment of manufacturability and expected yield based on probability distributions. Designers need new ways to assess the relative importance of DRC violations and DFM improvement recommendations to make optimal trade offs between time to tapeout, device performance and manufacturing cost.

Finally, the trend towards larger designs puts pressure on testing time that requires ever more test compression. In addition to testing, improvements to manufacturability require robust diagnostic yield learning systems that can identify failures that are currently attributed to random particle deposition.

Design for manufacturability through the IC flow

The current state-of-the-art is to automate straightforward layout enhancements, such as wire spreading, metal fill, via doubling and via enclosure extensions, wherever DFM analysis identifies potential litho, CMP or random defect hot spots. However, leading-edge process nodes require DFM-based layout optimization to ensure accurate timing, power and SI closure while also introducing improvements to ensure manufacturability. The place-and-route timing engine should incorporate realistic as-manufactured physical dimensions into the layout optimization process itself rather than waiting until layout is complete - also referred as correct-by-construction design. This requires very fast, "real-time," signoff quality DRC/DFM analysis running concurrently during place-and-route optimization. For example, inclusion of fast litho analysis can guide the router to prevent "litho-unfriendly" patterns from being created in the first place. Similarly, availability of critical area analysis (CAA) and CMP within place-and-route allows the router to perform more global and intelligent wire spreading, widening and metal fill as the layout is being constructed, rather than as ECO fixes.

Achieving acceptable yield at 45 or 32nm requires optimizing for lithography, CAA and other DFM metrics in conjunction with each other. For example, optimizing a design for CAA without also considering lithography effects will probably result in a sub-optimum solution. One practical demonstration of this requirement is via doubling. If only the CAA constraints are considered by your software when inserting redundant vias, the results could be worse from a lithographic perspective than if there was no via doubling at all. To manage this "inter-optimization" of multiple effects, you need a comprehensive place-and-route solution that provides a framework for integrated analysis and optimization of the different effects.

Besides making the signoff process more predictable, doing DFM optimization during design has inherent advantages. For example, the timer knows which paths are the most critical for timing and SI, so it can take special care to minimize parasitic side effects when doing metal fill around these paths. Along with being DFM-driven, an ideal place-and-route system must also handle multiple operational modes (e.g., power-down modes, scalable voltage and clocking), and environmental factors such as external voltage and temperature swings. The timing engine needs to know timing cost, litho cost, etc., and take them all into account while maintaining sign-off quality layout. In this manner, the place-and-route tool will be able to create an optimized design that results in a minimum of violations at the post-processing stage.

Nevertheless, some violations will remain at the physical verification (PV) signoff stage. At this point, time and accuracy are key objectives. DRC runtimes are shorter with tools that use improved data structuring, hierarchical processing, more efficient memory usage, multithreading and distributed computing. Verification time is also reduced by a shift from a sequential to a concurrent workflow model. In this approach to design rule fixing, the PV tool shows violations as they are discovered in a DRC run, along with visual aids to help the designer quickly locate and repair the source of the violation. After making a fix, the designer can immediately initiate a parallel DRC run to ensure that the fix has not caused any new problems.

Another strategy to improve the DFM flow is to view design rules as a spectrum from the traditional "hard" rules, whose violations must be removed before tapeout, to "soft" or recommended rules that improve the manufacturability, and hence the expected yield, of the design. There tend to be many more recommended design rule (RDR) violations than hard DRC violations during signoff, and the challenge facing the designer is to decide which of the RDRs should be followed, and which of the violations should be repaired. This comes down to a tradeoff between time-to-market and manufacturing yield, and PV tools should provide a "DFM score" that gives the designer a gauge of manufacturability (see Figure 2). Over time, DFM scores can be correlated to actual manufacturing yield to help close the loop between design and manufacturing output, a process often referred to as "improvability."

Figure 2. Prioritizing DFM enhancements.


After PV and tapeout, masks still need optical corrections. OPC software must be accurate, and have a large data capacity. Two recent advances in OPC technology include dense modeling and co-processor acceleration (CPA). Dense modeling evaluates the layout geometry on a high-resolution grid. This makes the analysis more accurate by evaluating more points in the design, and by accounting for interactions of closely-spaced features more effectively. This is an improvement over sparse models that look only at specific points of a feature, for example, line ends and corners. Dense modeling is more accurate, but far more computationally intensive, so the algorithms must be very efficient. Fortunately, dense modeling lends itself to acceleration by hardware processors that are purpose-built for numerical calculations, such as the IBM Cell/B.E. processor. By optimizing OPC software for mass-produced CPA platforms, suppliers can deliver high accuracy and performance at a relatively low cost compared to custom hardware.

Current practice after tapeout and signoff is to transfer GDSII data to mask resolution and enhancement. But design information should also be fed forward to communicate design intent and performance requirements. Use of design information helps prioritize and focus optimizations on the most critical parts of the circuit.

After fabrication is the time to gather statistically relevant data on yield. Testing systems need compression technology that allows more testing with fewer patterns for large SOCs. Along with detecting failed die, testing should also include test diagnosis to determine the root cause of failures using design data and results from various stages of testing. Advanced test failure diagnosis can provide the location and classification of defects. Through statistical analysis, related failures can be grouped, exposing failure patterns that appear as random defects without the added information. The results of volume diagnosis, validated by failure analysis, can then be fed back to improve the design or process, resulting in yield improvements throughout the whole IC lifecycle (see Figure 3).

Figure 3. Closed loop between design and test.


Starting at 90nm, each successive node in the nanometer IC era requires that design and manufacturing be brought ever closer together. At 45nm, the issues of manufacturing process variation and interdependency of design metrics become impossible to manage with existing design tools. Design teams need to adopt new tool flows and methodologies that close the "design-to-silicon" loop. Yield and variability must be addressed through a complete design flow, starting with DFM-aware place-and-route, through advanced sign-off verification, mask preparation, testing and defect diagnosis.

By Sudhakar Jilla and Jean-Marie Brunet.

Sudhakar Jilla and Jean-Marie Brunet are with Mentor Graphics Corp.

Go to the Mentor Graphics Corp. website to learn more.

Keywords: SOCcentral, Mentor Graphics, design for manufacturing, design-for-manufacturing, DFM, design for yield, design-for-yield, DFY, ASICs, ASIC design, EDA tools,
488/26728 9/2/2008 9116 9116
Add a comment or evaluation (anonymous postings will be deleted)

Designer's Mall
Cinco De Mayo countdown banner
0.96875



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Progressive Static Verification Leads to Earlier and Faster Timing Sign-off


Graham Bell
VP of Marketing,
Real Intent

Executive
Viewpoint

Threading the Way
through
SOC Verification


Thomas L. Anderson
VP of Marketing,
Breker Verification Systems

Odd Parity

What? You Haven't Made Any Resolutions?


Mike Donlin
The Write Solution

Odd Parity Archive

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  1.0625