September 2, 2008 -- The semiconductor industry has long recognized the growing issues of manufacturability and wider parameter variations at the deep, sub-micron process nodes. Many EDA startups that developed capable DFM point tools, which focused on only a part of the problem, have recently been acquired by larger EDA companies that integrate these tools into a more comprehensive DFM solution. But the integration of DFM tools into a robust design flow takes time, so today, well-integrated DFM solutions remain scarce, except for a few proprietary DFM tool sets offered directly by silicon foundries.

At 65nm and above, DFM solutions provided incremental yield improvements in manufacturability by applying optional, but recommended, guidelines at the nominal process condition. These DFM rules usually became less stringent as the manufacturing process matured over time. But at 32nm and below, the product can be non-functional or the yield insufficient for high-volume production without mandatory DFM sign-offs that are based on a combination of DFM rules and accurate DFM models that are statistically calibrated against the full process window.

Today's SOC designers, however, are insisting on more practical and comprehensive DFM solutions than ever before. That's because a complex SOC now is composed of digital, analog, RF, low power, multi-core processors, memory, peripherals, and sophisticated, high-speed interconnect architectures, which are commonplace on high-volume, consumer products. Furthermore, the shorter development times demanded by shrinking market windows, the increased focus on proven, third-party IP to lower the functional risk, and the mandate to make the design more robust against larger manufacturability margins requires that DFM takes a more central role in deep, sub-micron chip design.

Unfortunately, every segment of the semiconductor supply chain is now approaching a crisis in DFM:

Many designers lack flexibility and choice for best-in-class DFM solutions which can utilize blocks from multiple IP providers, and DFM tools from multiple vendors, to produce chips that can be manufactured across multiple fab lines or foundries. IP providers lack a standard DFM infrastructure to avoid redundant re-design and re-work to support their customers, and lack the ability to pass well-defined DFM parameters between all the tools used for DFM analysis and optimization. The cost to build and qualify a full compliment of accurate DFM models for critical area, litho, CMP and routing using statistical parameters for multiple foundries continues to rise. From the silicon foundry side, the production of thousands of Process Design Kits (PDKs) with unique interfaces to multiple tools from several EDA vendors is rapidly becoming an unbearable and unjustifiable burden. The growing PDK development cost measured in time and human effort pitted against the shrinking market windows for fabs to generate an ever increasing multitude of PDKs each year for DFM point tools is becoming inefficient and unsustainable.

A shared vision

Open standards become an absolutely necessity for DFM solutions that encapsulate multiple EDA tools from multiple vendors and multiple IP blocks from multiple providers which target multiple foundries. Cross-fab manufacturing of high-volume products, third-party IP and mandatory DFM sign-off criteria across a variety of manufacturing and design interfaces requires a DFM infrastructure that is more open, inclusive and flexible than what exists today. The alternative is to use a proprietary DFM solution with qualified IP that targets only a single foundry, thus limiting one's design and manufacturing choices.

Model-based DFM requires accurate optical/ resist/ etch models for critical area and litho which must interoperate with the reticle enhancement technology (RET) used to manufacture the masks for production. Chemical metal polishing (CMP) models require calibration of metal density variations with thickness of films and inter-layer insulators. Statistical models require the modeling of the Ion and Ioff of transistor currents (which can vary by more than 35% depending on the transistor's surrounding context).

The semiconductor industry has the opportunity to grow and be economically healthy, with more end users who have more choices in how they build their products and with more confidence for high-volume production across multiple foundries. Targeting multiple foundries lowers both risk and production costs. Interoperability and integration across design and manufacturing interfaces provides foundries and end users with the flexibility and choice to produce DFM solutions which are more cost effective and enable a more efficient and healthy market.

Historically, DFM models have been optimized for the nominal process because manufacturing variations were well localized around the nominal process condition. But the wider manufacturing variations at the deep sub-micron process nodes, means that DFM optimizations must use the statistics of the entire range of process conditions and not just the nominal condition. Full, process-window manufacturability requires the design to be more robust across multiple process conditions which may not be the best correction any single process condition including the nominal process condition.

Finally, because companies across the semiconductor supply chain have developed specialized and highly valuable intellectual property, this new DFM infrastructure must be implemented such that the embedded IP, regardless of whom it belongs to, can be protected/ encrypted even as the interfaces and semantics are shared across the design space.

DFMC leaders create an interoperable solution

The Design for Manufacturability Coalition (DFMC) is an open industry effort operating under the auspices of Si2 to solve the emerging DFM interoperability crisis. The goal of the DFMC is to build the infrastructure for an Open DFM solution with multiple IP, multiple DFM tools, targeting multiple foundries with statistically based DFM repairs and optimizations. DFM sign-off in sub 32-nm design flows will need to be as central as functionality, power and timing sign-off are today, and the DFMC is developing open technology to enable this objective.

The DFMC has assembled an impressive steering committee with highly-regarded members who are acclaimed as industry thought leaders in the application of DFM to high volume, production flows. In addition, the DFMC works closely with leading universities, other standards bodies and industry consortia such as STARC and the Common Platform Alliance. The DFMC includes representation from all corners of the chip design eco-system and has already received several important technology contributions which will become the basis of its standards. All of the contributed technology is already being used in production, and it was contributed in accordance with proven legal agreements for safe adoption. The initial focus has been to define open DFM model parameters for optical, resist, and etch with different RET recipes for shape bias, OPC and Sub Resolution Enhancement Features (SRAF).

The current DFMC anchor project will demonstrate the ability for multiple analysis and optimization tools to use the shared technology to avoid, detect and repair litho, critical area and routing hotspots. Using shared interfaces, multiple analysis tools can communicate the location, type and recommend edge movements to DFM optimization tools in order to repair the hotspots, and to train the DFM aware implementation tools to avoid them in the future. The anchor project extends proven DFM technology contributed by our members by defining a standard semantic, syntax, statistics with calibration data for the top five DFM yield limiters: critical area, CMP, litho, routing and parameter variation.

Next year, the DFMC will focus on CMP and routing models that take into account statistical parameter variations in timing, power and noise. There is plenty of opportunity to join these thought leaders and influence this emerging DFM standard infrastructure.

The DFMC is open to all interested parties under strictly non-discriminatory terms. For more information, and a list of all current DFMC members, visit the Si2 website.

By Jake Buurma.

Jake Buurma currently serves as VP of West Coast Operations for the Silicon Integration Initiative (Si2). Buurma has more than 33 years of industry experience equally split between the design of integrated circuits at major semiconductor companies such as National Semiconductor and Toshiba Semiconductor and developing EDA software at companies such as Cadence Design Systems, Silicon Navigator and Aprio. Jake has worked extensively with global development teams in automated physical design, EDA software development and improving Design for Manufacturability (DFM) at sub-100nm process nodes.