October 6, 2008 -- According to the International Technology Roadmap for Semiconductors 2007 [1], the percentage of memory in CPU cores ranges from 65 to 75% and from 83 to 86% in consumer cores. For an SOC design, memory density is higher than logic, which means the chance to have a defect is higher in embedded memory. The quality of embedded memory can dominate overall quality and profitably of the whole chip. Thorough testing ensures that customers receive only high-quality devices, and memory repair — through redundancy selection — can greatly improve yield and profitability.

Industry analysis indicates that memory yield can be improved from 5 to 20% and chip yield from 2 to 10% if redundancy is implemented for memory repair [2]. Normally, a memory IP vendor provides redundancy allocation for memories beyond a certain size, which is determined by a yield equation — for example, at least one redundant column for every 1Mb or one redundant row for every 4Mb. In general, the amount of redundancy depends upon the memory’s redundancy architecture, the desired yield improvement, the defect density, and chip area constraints.

Testing strategy

The use of a wide variety of memory structures, along with their performance and area overhead requirements, means that a test strategy with multiple tactics must be applied (see Figure 1). To test small memory arrays or registers that are performance-critical, existing scan chains can be used for macro-testing. However, medium to large memories warrant the use of memory built-in self test (BIST) to apply a suite of test pattern algorithms. In many cases, BIST controllers can be shared across multiple embedded memories to reduce both area and test time. For the purpose of identifying yield-limiting mechanisms, failure diagnosis circuitry may be added to localize faulty memory cells.

If memory repair is going to be implemented, it must be done with an eye on manufacturing costs. In these circumstances, it is important to have a memory test flow that will:

Detect memory failures, Efficiently determine which rows/columns need to be repaired, Automate redundancy selection and fuse programming, Re-test the device to ensure the repair is successful.

Figure 1. Embedded memory test strategy.

BIST

Memory BIST adds a layer of test circuitry around memory. This interface addresses controllability and observability challenges to enable thorough testing of every structural element of embedded memories. BIST adds an internal finite-state machine (FSM) that acts as a dedicated tester, greatly reducing external test requirements.

Figure 2. Memory BIST.

BIST includes a “wrapper” that inserts test multiplexors into functional paths (address, data, and control) to enable complete control of the memory. The FSM orchestrates a test procedure that applies a sequence of patterns, reads them back from the memory, and then compares them. After the test, a flag is set to indicate pass or fail (see Figure 2). Intricate sequences of patterns that are used to expose subtle defects are called the memory test “algorithms.” Automated flow, flexible algorithms, and pipelining support for high-speed testing are critical factors to the success of a high-performance design [3].

BIST provides a low-cost memory test strategy while actually improving test quality. It eliminates the need for external test patterns, reducing tester application time. Further, it is much easier to execute tests at speed because of the proximity of the BIST circuitry to the memory.

A BIST controller can be very valuable during failure diagnosis because it can pinpoint the defective memory cells and download the failing data on every occurrence of mis-compares while applying the test patterns. Compared with default pass/fail mechanisms, this diagnosis capability provides the information necessary for silicon debugging. The entire mechanism can be accomplished with minimal effect of silicon area and routing overhead.

To solve the bandwidth discrepancy between the at-speed BIST and the inherently lower tester clock speed, a diagnosis clock can be implemented in the BIST controller; that is, higher speeds can be used in testing but slower speeds can be used for shifting failure data out to the tester.

BISA

Built-in self analysis (BISA) is an added function that can facilitate memory repair. BISA alleviates the challenge of dealing with large volumes of failing data by analyzing the location of one or more defects and identifying which structures (typically row or columns) need replacement. With this information, defects can be bypassed by re-selecting the memory access path to a spare row or column (see Figure 3). When BISA executes, it first determines if the memory array is defect-free, repairable, or unrepairable. When multiple redundant resources are available, repair algorithms determine how best to apply the redundancies to maximize yield.

Figure 3. Block diagram of BIST and BISA.

Repair approach

Once BISA is implemented, a few different approaches can be used to execute a repair operation. The repair operation essentially switches in the redundant resources in place of the defective portion of the memory array. Initially, hard or soft repair methods have been used, but a more recent method of electrical fuse repair is becoming widely used because it requires fewer manufacturing steps and simplifies the test flow.

The hard repair method has been used by commodity memory vendors for years. It selects redundancy through laser-blown programming with a diffusion fuse. However, this method can have significant cost overhead because of extra manufacturing steps. With this method the memory must first be tested and defect rows/columns are identified for repair. Then a separate manufacturing step is required to laser-trim the appropriate fuses. Finally, the device must be put back on the tester to verify that the repair was successful.

Unlike a repair signature stored in a non-volatile element for hard repair, soft repair stores the repair configuration in a volatile element, such as flip-flops or scan registers. Because of this, the device must execute the BIST, BISA, and repair every time the device is powered-up. The main drawbacks with this method are that it is unable to mimic operational corners — such as high temperatures or high voltage — that are executed on the test floor when converting and writing the data, and the chip must be designed so that the device is put into a particular test mode for these conditions each time it’s powered up.

Electrical fuse repair

Electrical fuse repair offers a significant advantage over laser-fused hard repair and soft repair approaches in terms of savings in manufacturing steps — only a single insertion is needed and the separate fuse blowing operation is eliminated. This method is quickly becoming the standard methodology for memory repair — it doesn’t require BIST and BISA to be run each time at power-up like soft repair. Electrical fuse repair also has other advantages: smaller area overhead, no risk to adjacent devices, better scalability with process variation, and no requirements for specialized equipment [4].

TSMC offers electrical fuse IP (eFuse) suitable for repairing memories with redundant resources. It’s a non-volatile, one-time programmable procedure based on a silicided poly fuse process [5]. The eFuse IP can be programmed from BIST/BISA information, allowing the memory reprogramming to be performed once and saved permanently.

Automation flow for electrical fuse repair

From a system integration perspective, generating interconnections among different cores can be difficult [6]. The BIST/BISA logic, eFuse IP, and repairable memory must all be properly inserted. Fortunately, commercial tools can generate all interconnection logic automatically, including the required data converter, write controller, and read controller (see Figure 4). By using automated tools, you can seamlessly generate and insert memory BIST or BISA that is fully compatible with TSMC eFuse IP and repairable memory. Insertion can be done at the RTL or gate level. BIST control patterns (i.e., WGL and STIL) for individual controllers are brought to the top level. And for verification, a top-level test-bench is created.

Figure 4. Block diagram of BISA and eFuse.

Figure 5 illustrates two sets of operations. The test-and-repair flow is performed during manufacturing, and repair is powered on in the field. During manufacturing, the proper fuses for repair are determined and blown. After BIST tests the memory, BISA reports the repair data, and a converter changes BISA repair data format to the memory specific format. Then the converted data is written into the eFuse IP. At that point, the tester will supply a programming voltage and the eFuse is blown. After the programming, the repair data is read out from eFuse IP and shifted into repairable memory. The BIST is rerun after repair to ensure the operation is successful and to make sure no defective cells were included in the redundancy.

Figure 5. The test-and-repair flow is performed during manufacturing, and repair is powered on in the field.

Once programming is completed in manufacturing, the data is stored in the eFuse. Each time the device is powered on, the data is read out directly and shifted into repairable memory. The reason for implementing the power-on repair is because memory redundancy selection will deactivate each time the supply power is turned off. The next time the chip is powered on, redundant resources need to be activated again to select the appropriate array elements.

To summarize, the automated electrical fuse approach:

Requires less manufacturing steps than hard repair alternatives, Requires no specialized equipment — programming is done with standard testers, and Has low silicon real estate overhead.

All these factors make the electrical fuse memory repair strategy practical and cost-effective.

Summary

Managing yield in advanced technology nodes is critical. Repairable memory can be very effective in improving yield. An approach using electrical fuse repair has the advantages of low cost and high reliability. By working with a foundry that provides repairable memory IP, EDA vendors can provide chip designers with an integrated flow that automates the memory testing and repair process in an integrated manufacturing flow, reducing risk and improving productivity and manufacturing yield.

By Ting-Pu Tai

Ting-Pu Tai is a business and marketing development manager for the design-for-test product division at Mentor Graphics Corp. He has worked in the test area for the past eight years, and before joining Mentor Graphics, he worked for Acer Laboratories and Philips Semiconductors.

References

1. International Technology Roadmap for Semiconductors 2007 Edition, Test and Test Equipment.
2. "Design and Test of Large Embedded Memories: An Overview," Rochit Rajsuman, IEEE Design & Test of Computers, 2001.
3. "BIST for Deep Submicron ASIC Memories with High Performance Application," T.J. Powell, Wu-Tung Cheng, et al., International Test Conference, 2003.
4. IBM System z9 eFuse Applications and Methodology, January/ March 2007.
5. TSMC’s Electrical Fuse IP (DSD-ElectricalFuseIP.pdf).
6. “Verification Methodology for Self-Repairable Memory Systems,” Jin-Fu Li and Chun-Hsien Wu, Asian Test Symposium, 2006.