October 20, 2008 –– Calypto Design Systems, Inc. has added new sequential power optimizations and support for VHDL designs to its PowerPro CG (clock gating) automated register transfer level (RTL) power optimization solution.

Support for VHDL in PowerPro CG extends the benefit of power savings to more designers, in particular those in European consumer and wireless electronics companies where VHDL is the dominant design language. PowerPro CG automatically reduces power by reading a synthesizable RTL design captured in VHDL or Verilog and generating a RTL design identical to the original design with additional clock-gating enable logic.

"With each release of PowerPro CG, we have added powerful new sequential optimizations and enabling features such as VHDL support," says Tom Sandoval, Calypto’s chief executive officer. "PowerPro CG has reduced power on hundreds of designs, across multiple applications worldwide and is the only fully automated RTL power-optimization product on the market."

PowerPro CG identifies sequential clock-gating enable conditions based on Calypto’s patented Sequential Analysis Technology. The new sequential optimizations added to PowerPro CG save additional power in heavily clock-gated RTL code, such as existing consumer and wireless designs that previously have been optimized manually. The latest release of PowerPro CG finds clock-gating enable conditions beyond those already present in the design. The output of PowerPro CG is comprehensively verified with sequential equivalence checking to ensure no functional changes are introduced.

The latest PowerPro CG release includes leading-edge graphical display and navigation features in the PowerPro Analyzer. These capabilities allow designers to thoroughly understand the sequential nature of the power optimizations added to their RTL code by PowerPro CG.

Availability and Pricing