| Planning, Adopting and Implementing Adaptive Reuse | Publication: EE Times EDA Designline Contributor: Integrated Device Technology, Inc. (IDT)
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November 18, 2008 -- It has been mentioned that during the rough-and-tumble days of 1950s Chicago politics, a ward boss asked an Adlai Stevenson volunteer who sent him to help in the campaign and when the response was nobody, he quickly replied: "We don't want nobody nobody sent." It is the same with reuse in that nobody wants reuse no one reuses. If you have to question the reuse benefit, then you should not spend resources making anything reusable. Similarly, no convincing is necessary when reuse becomes a practice weaved into the design process such that when it is built, it gets used with cool efficiency.
The reuse imperative (where the developer and implementer are two separate entities) has potentially two separate goals, depending on whether the point of view is from the reuse content developer or the reuse content consumer. The developer perspective considers implementing the most universal and versatile solution to maximize dissemination and sale, while the reuse consumer wants the solution that provides the most differentiation with unique features not easily reproducible and may be willing to give up reuse to maintain the value-add that is hard to reproduce.
One way to reconcile those two conflicting necessities is to develop adaptive, reconfigurable approaches that allow single development with multiple, user-modifiable uses. A memory compiler is a perfect example of a design-once, retarget-multiply-without-compromising differentiation. With this in mind, creating environments that lend themselves to reuse and retargeting can provide the optimal solution for reuse and value maintenance while helping productivity. To complete the picture, one has to be aware as to whether the reuse is applied pre-silicon or if the reuse is intended for post-silicon reconfiguring. Field programmable gate array (FPGA) and tunable/register or software programmable options are examples of post-silicon reuse.
By Camille Kokozaki. (Kokozaki is Director of Design Automation Services at IDT.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
| | Keywords: EE Times EDA Designline, Integrated Device Technology (IDT), ASICs, ASIC design, IP, intellectual property, cores, FPGAs, field programmable gate arrays, FPGA design, reuse, EDA tools,
| | 580/27417 11/18/2008 7829 325 | |
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