February 3, 2009 -- Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or best-case fast process and operating corner conditions typically used during the STA correspond to the extreme 3s corners. This forces overdesign, leaving a lot of margin on the table in terms of chip power, area and performance. As a result, most of the manufactured parts can operate at higher speed and dissipate much less power than the value supported by the package design.
Statistical static timing analysis (SSTA) helps address this problem, allowing the design team to make tradeoffs in terms of performance and the roll-off at the process extremes. An overview of the SSTA is presented in this article.
By Rakesh Chadha and J. Bhaske. (Chadha is Director of Design Technology at eSilicon Corp. and Bhasker is an expert in the area of hardware description languages and RTL synthesis. He has been the chair of two working groups: the IEEE 1076.6 VHDL Synthesis and the IEEE 1364.1 Verilog Synthesis.)
This brief introduction has been excerpted from the original copyrighted article.