Page loading . . .

  
 You are at: The item(s) you requested.Monday, May 20, 2013
Identifying IP cores to Protect Your Investment  
Publication: Design & Reuse
 Printer friendly
 E-Mail Item URL

January 26, 2009 -- IP core providers are increasingly aware of the need to protect their investment from either unintended or unlicensed usage of their IP core blocks. This would require identification of IP core blocks from any SoC. IP core identification is not a trivial task and it involves different approaches depending on the nature of IP cores.

In this paper, Semiconductor Insights shows some noble ways of identifying IP cores from any SoC products to protect the interest of IP core providers. Techniques developed by Semiconductor Insights to identify IP core blocks include methods such as circuit extraction using advanced delayering techniques, layout comparisons, automatic recognition and extraction of standard cells and blocks of designs, netlist generation from the extracted circuits, use of circuit library to identify IP blocks, use of structural data mining algorithm for netlist comparison, and device and system level testing to identify IPs involving algorithms and system level protocols.

By Jason Abt, Val Gont, Vyacheslav Zavadsky, and Young Choi. (All are with Semiconductor Insights, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

Keywords: Design & Reuse, IP, intellectual property, cores, ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design,
590/27991 1/26/2009 6153 298


Designer's Mall
0.15625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.25