February 23, 2009 -- Design reuse and IP-based design are established design practices enabling fast integration of large-scale, high-complexity systems. But while silicon potential keeps improving through node shrinks, designs meant for reuse cannot leverage these technological advances due to their rigidly defined micro-architecture.
In this article we present a design methodology based on high-level synthesis that allows retargeting functional IPs in the form of C++ programs to technology optimized RTL implementations. We will expose results that show that this approach can eliminate the usual compromise of design quality versus design time imposed by design reuse strategies, yielding optimal implementations in very short time.
By Thomas Bollaert. (Bollaert is with Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
