March 11, 2009 -- It is increasingly common for complex programmable logic devices (CPLDs) to be used in systems with stringent power budgets. Examples include smart phones, handheld instrumentation, video recording equipment, and navigation devices. Although a number of "zero power" CPLDs exist with standby power measured in microamps, these devices often don't have the features required for a particular design. In these cases, power supply cycling offers designers a viable means to achieve the desired features as well as low power consumption.
By Gordon Hands. (Hands is Director of Strategic Marketing for Lattice Semiconductor Corp.'s Low Density and Mixed Signal Solutions.)
This brief introduction has been excerpted from the original copyrighted article.
Keywords: EE Times Programmable Logic Designline, Lattice Semiconductor, CPLDs, complex programmable logic devices, power analysis, power optimization, low power design, low-power design, FPGAs, field programmable gate arrays, FPGA design,
