Page loading . . .

 You are at: The item(s) you requested.Friday, October 21, 2016
Debug and Testability Features for Multi-Protocol 10G SerDes  
Publication: Design & Reuse
Contributor: Prism Circuits, Inc.
 Printer friendly
 E-Mail Item URL

March 9, 2009 -- The article describes the design-for-test (DFT) features of a 10.3125Gbps SerDes and other such high datarate IP as XAUI, PCIe, and others. It is shown that extensive testability can be implemented in a high data-rate Serdes. The paper describes the bench-test and characterization features, as well as wafer and production test considerations. The SerDes is compliant to IEEE 802.3ap. The DFT features include IEEE 1149.6 AC boundary scan, PRBS generators and checkers.

Methods for observing both internal analog and digital nodes inside the Serdes are discussed. Loopback circuitry includes an on-die "stressed-eye" feature that can adjust both the amplitude and timing of the loopback waveform through a programmable code. An internal eye monitor features allows the system designer to view the eye as it is seen by the receiver.

By Claude Gauthier, Shaishav Desai, Karthisha Canagasaby, Kuo-Chiang Hsieh, Chethan Rao, Alvin Wang, and Sanjay Dabral. (All are with Prism Circuits, Inc.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the Design & Reuse website.

Read more about
Prism Circuits, Inc.

Keywords: Design & Reuse, Prism Circuits, ASICs, ASIC design, SerDes IP, intellectual property, cores, design for test, design-for-test, DFT, EDA tools,
590/28333 3/9/2009 10316 543
Designer's Mall

Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.28125