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Debug and Testability Features for Multi-Protocol 10G SerDes  
Publication: Design & Reuse
Contributor: Prism Circuits, Inc.
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March 9, 2009 -- The article describes the design-for-test (DFT) features of a 10.3125Gbps SerDes and other such high datarate IP as XAUI, PCIe, and others. It is shown that extensive testability can be implemented in a high data-rate Serdes. The paper describes the bench-test and characterization features, as well as wafer and production test considerations. The SerDes is compliant to IEEE 802.3ap. The DFT features include IEEE 1149.6 AC boundary scan, PRBS generators and checkers.

Methods for observing both internal analog and digital nodes inside the Serdes are discussed. Loopback circuitry includes an on-die "stressed-eye" feature that can adjust both the amplitude and timing of the loopback waveform through a programmable code. An internal eye monitor features allows the system designer to view the eye as it is seen by the receiver.

By Claude Gauthier, Shaishav Desai, Karthisha Canagasaby, Kuo-Chiang Hsieh, Chethan Rao, Alvin Wang, and Sanjay Dabral. (All are with Prism Circuits, Inc.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the Design & Reuse website.

Read more about
Prism Circuits, Inc.

Keywords: Design & Reuse, Prism Circuits, ASICs, ASIC design, SerDes IP, intellectual property, cores, design for test, design-for-test, DFT, EDA tools,
590/28333 3/9/2009 10061 460
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