March 19, 2009 -- You have to design in power-rail filtering to meet the manufacturer’s specifications for output clock jitter in phase-lock loops (PLLs) and crystal oscillators. There are two types of power sources, voltage and current. A voltage source keeps its output voltage level constant and presents a low-impedance output. A current source keeps its output current constant with a high-impedance output. A decoupling component is a two-pin device that provides a low impedance path between the power rail and ground. This gives a local storage of energy to service sudden current demands by the target load. A filter is a three-pin device that alters the transmission of a signal by enhancing or suppressing some of its frequency components.
The output clock quality of a phase-lock loop circuit is highly sensitive to power supply noise. IC manufacturers define PLL power filtering requirements by specifying the maximum voltage noise ripple at the power pins, say, 10mV, as well as the filter attenuation of such noise as a function of the frequency, perhaps -3dB at 50 kHz. You should increase the power-rail impedance between the voltage source and the PLL circuit load by placing a current source between them. The filter should also provide a dedicated voltage source to the PLL load.
By Rick Rabinovich. (Rabinovich is a senior principal hardware engineer at Alcatel-Lucent.)
This brief introduction has been excerpted from the original copyrighted article.