April 27, 2009 -- Currently all traffic arriving from I/O ports (e.g., network port or storage port) to server/ appliance, passes through the platform hub (chipset) and is sent to the server processor(s)/ core(s). The processor that receives the data is responsible for classifying and directing data frames to their final destination. This destination can be another I/O agent, either a network port or local/remote storage (i.e., disk).

In most cases the server processor only needs to inspect and process a small portion of the data frame (header or header fields), or even make automatic decisions (i.e., send compressed packets to decompress engine).

Due to the current nature of I/O traffic, all frame data is sent to the processor(s), resulting in the following:

Increase traffic via the platform hub bus interface (PCIe or HT) Increase traffic towards the processor host memory (in NUMA architecture) or towards the host shared memory (in non-NUMA architecture) Increase cache pollution caused by redundant data loaded to the processor cache Increase processing latency as more data is written to the host memory which in turn, becomes a bottleneck Increase power consumption due to increased access to the host memory, more traffic on local bus, more processing on processors, etc.

Due to the introduction of multicore/ multi-processor environments and the increase in I/O BW from networks and storage, currently with network ports of 10Gbps, and 40Gbps and 100Gbps in the future.

The overall effect is that most users discovered that their I/O performance did not scale well after moving from a single processor single core to a multi-processor multi-core system. Moreover, they found it difficult to scale their system to process and handle traffic in the range of 10Gb/s and higher.

To solve the problems described herein, we recommend improving platform architecture, making it the base for future chipsets. The improved architecture is based on content aware routing of incoming traffic. As part of our solution, we will first address the previous and current generations of platform architecture.

By Yehiel Engel. (Engel serves as Chief Architect, Commex Technologies.)