June 11, 2009 -- Four to five years ago, the hype surrounding design-for-manufacturing (DFM) technology for advanced system-on-a-chip (SOC) design was near insufferable. At that time, 90 nm was the state-ofthe- art process node and most fabless houses were preparing for a shrink down from the 130-nm node. And without some way of feeding process parameters back into the design side, the likelihood of any chip yielding at 90nm was slim to none.

This set off a bit of panic among the design community on the one hand and a feeding frenzy among venture capitalists and would-be DFM startups on the other. Indeed, a rather large number of startups emerged in the DFM space. Almost any tool that touched the back end was being called a “DFM” tool for one reason or another, speciously or not. Just as quickly, a backlash from the DFM-have-nots arose, with accusations of "design for marketing" hurled at those who didn’t fit into the more rigorous definitions of what DFM was supposed to be about. Today, with the 65-nm node firmly entrenched and foundries ramping up their 40-nm processes, the DFM picture has changed quite a bit.

The hype isn’t as strident these days, but that doesn’t mean it isn’t an essential element of SoC/ASIC implementation flows. In fact, it’s more vital than ever and will become more so with the coming process shrinks to 40nm and below. DFM is even becoming a factor in analog/mixed-signal flows for RFICs.

By David Maliniak, Electronic Design Senior Editor