June 24, 2009 -- Zocalo Tech, Inc. is shipping Zazz, first introduced at DVCon in February 2009, to make using assertion libraries quick, easy and accurate by automating tedious error-prone tasks with its intuitive graphical user interface (GUI). With Zazz, says Zocalo, the checkers from the most widely used assertion libraries can be attached to a design and documented in minutes.

Zazz is Linux-based and supports any mix of Verilog 1995, Verilog 2001 and SystemVerilog design files. The Zazz front-end includes an incremental parser, elaborator and design viewer. An existing design or new design can be read into Zazz where it is parsed, elaborated and graphically displayed. The design may then be modified with the editor of choice without leaving Zazz. The design viewer provides superior design presentation and navigation. When a design is modified and saved, it is incrementally parsed and elaborated. The incremental feature, along with the built-in modification monitoring quickly updates the graphical display and gives immediate feedback about errors. The Zazz front-end provides designer productivity advantages even when assertion libraries are not being added or used.

"Nearly all designers can add assertion checkers manually," notes Howard Martin, Zocalo President. "This rarely happens because the time required for creating, debugging, attaching and documenting them is difficult to justify when considering the typical chip-design schedule. The availability of assertion libraries reduces that time, but not nearly enough for wide scale use by designers. With Zazz, attaching and documenting the library checkers that cover most of the designer’s requirements, takes less than a minute each. This level of productivity and the low cost of Zazz make designer provided assertions highly effective."

Integrated with the Zazz front-end, Assertion Library Support software provides:

Ease of selecting checkers from assertion libraries. Ease of binding the checkers to the design file. Ease of configuring the checkers. Ease of exportation and management of bind files. Automatic creation of verification plan documentation.

Support is provided for Accellera’s Open Verification Library (OVL), Cadence’s Incisive Assertion Library (IAL), Mentor’s Questa Verification Library (QVL) and Synopsys’ SystemVerilog Assertions Checker Library with Coverage Level Reporting.

Availability and Pricing