June 15, 2009 -- A variety of factors – from the micro to the macro, from conserving battery life to lessening global warming – has pushed power conservation rapidly up the list of system designers’ concerns. Engineers have ranked power consumption first in recent surveys on key design priorities or as a close second next to performance, density, and cost.
FPGAs present unique challenges when it comes to power consumption. Armed with a good understanding of these challenges and new technology, techniques, and tools to meet them, system designers can realize the advantages of an FPGA-based portable system deployment. This is increasingly crucial as FPGAs are depended on more and more to provide flexibility and fast time to market in an expanding universe of applications.
Assessing a given FPGA architecture’s suitability for power-sensitive applications today warrants an in-depth examination of the power equation. We can do this by examining FPGA power characteristics and their effects before diving into optimization tools and possible design solutions, which include, among others, partitioning, clock and power gating, and voltage scaling.
By Fred Wickersham. (Wickersham is Product Marketing Manager, Software Tools, at Actel Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the DSP-FPGA website.
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