July 22, 2009 -- TSMC (Taiwan Semiconductor Manufacturing Company) today unveiled Reference Flow 10.0, the latest version of its design methodology to lower design obstacles, improve design margins, and increase yields. Reference Flow 10.0 is one of the key collaborative components of the Open Innovation Platform. The newest generation of the company’s reference flow continues the tradition of driving advances in design methodology, addresses new design challenges of 28-nm process technology and delivers innovations to enable system-in-package (SiP) design.
28-nm design enablement
TSMC’s Open Innovation Platform (OIP) paves the way for EDA tools to be ready for 28nm. OIP enables design and process technology co-optimization in the early stage of R&D, and ensures required EDA tool enhancements to happen correctly and timely. Specifically for Reference Flow 10.0, TSMC went beyond physical verification of DRC, LVS and extraction which heavily depend upon 28-nm process requirements, and engaged early with EDA partners to qualify their place and route tools for TSMC 28nm.
System-in-Package (SiP)
System-on-chip (SOC) has been the focus in the previous nine generations of the TSMC Reference Flow starting in 2001. Reference Flow 10.0 introduces SiP design solutions for the first time including SiP package design, electrical analysis of package extraction, timing, signal integrity, IR drop, and thermal to physical verification of DRC and LVS. These SiP technologies enable the exploration of implementation and integration strategies, realize end product design and strengthen competitive advantages in terms of cost, performance, and time-to-market.
Expanded EDA collaboration
New to the flow is a RTL-to-GDSII chip implementation track from Mentor Graphics, in support of customers’ EDA usage. Reference Flow 10.0 further enables existing ecosystem partners Altos, Anova, Apache, Azuro, Cadence, CLK DA, Extreme DA, Magma, Nannor, and Synopsys to bring EDA innovations to customers through collaboration with TSMC.
Differentiated features in power, performance and DFM
New low-power features in Reference Flow 10.0 include support for pulsed latch, a new low-power implementation scheme for power saving, and hierarchical low power automation, multi-corner power/timing co-optimization, multi-corner low-power clock tree synthesis (CTS), vectorless power analysis and more, enabling more effective power-aware implementation and power analysis. To drive greater performance, advanced stage-based on-chip variation (OCV) optimization and analysis is made available for the first time, enabling designers to get a more realistic look at timing for the purpose of removing redundant design margins. A new electrical DFM feature is introduced for designers to take into consideration the timing impact of "silicon stress effect," thus helping to increase yields.
Go to the TSMC (Taiwan Semiconductor Manufacturing Company) website to find additional information.
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