July 23, 2009 -- Much has been written in the past few months about the upcoming sunset of Moore’s Law. Stated succinctly, Gordon Moore predicted in 1965 that the number of transistors in ICs would double every 12 months1. There have been other versions of his prediction, including shifts to a performance metric and altered timeframes. However, the message is clear: a key metric doubles on a regular schedule and has for many years.
Moore has also stated that no exponential growth can continue forever, and it appears we are nearing the end of conventional silicon semiconductor scaling as we know it. Fundamental limits are being approached now both in planar silicon transistor technology and in on-chip interconnects. Furthermore, the costs for leading-edge photolithography have greatly accelerated as process nodes have shrunk.
Making faster transistors that are smaller and don’t leak when they’re turned off is getting extraordinarily difficult and expensive. They need to be good switches with low on-resistance and high off-resistance, and they need to change states very quickly. Despite the largely planar architecture of the process they’re made on, 45-nm generation transistors are highly complex.
Such transistors combine strain engineering and raised source/drain structures with exotic gate stacks employing high-K gate dielectrics and metal replacement gates as the control electrode . The 32-nm process node will continue to feature planar transistors, but what happens at the 22-nm node and beyond isn’t so clear.
By Richard Crisp. (Crisp is the Director of Semiconductor Technology and Applications for Tessera Technologies, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Design Magazine website.
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