July 13, 2009 -- Clock domain crossing (CDC) verification has become a critical component in ensuring correct design operations for complex SOC. CDC verification is not a nice-to-have checklist item any more for ASIC and FPGA design and verification teams. Adopting special technology for CDC verification has become a must-have item in the verification flow in order to ensure reliable chip operations in the field.
The reason that designers are concerned about CDC is metastability propagation, which is the root cause of all CDC failures. Metastability happens as a result of the domain crossing signal changing its value while being sampled within the setup and hold window of the receiving clock. Due to the asynchronous nature of the transmitting and receiving clocks, metastability is unavoidable. The key is to prevent metastability from propagating to the downstream logics, or in another word, to make sure that the domain crossing signals stay stable during the capture.
Jin Zhang. (Jin Zhangis technical marketing manager at Real Intent, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
