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New Flow for Automating Verification of ESD Design Rules  
Contributor: Mentor Graphics Corp.
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August 3, 2009 -- The high current of electrostatic discharge (ESD) pulses can cause severe damage to ICs, ranging from silicon and metal meltdown to gate oxide breakdown. With thinner oxides, thinner metals, shorter channel lengths, and multiple power supplies, newer technologies are becoming increasingly vulnerable to ESD damage. Modern ICs need more robust on-chip ESD protection circuits to maintain and improve chip reliability. [1–2]

ESD protection needs to be considered in conjunction with designing the core circuits. Designers typically follow a set of ESD-related rules during the design and layout of an IC. ESD design rules can be quite complex, especially for large ICs with multiple power or ground domains where interactions between circuit blocks result in many potential current paths [3]. Manually verifying these rules is time consuming and error prone so it’s highly desirable to automate the verification of ESD-related rules as much as possible. Also, because the ESD design rules vary based on design style and process technology, the verification method needs to be generic enough to work on different designs.

ESD rule checking tools [4–6] can detect common ESD design errors, such as violation of spacing requirements or compatibility issues between ESD devices and the circuit being protected. But they tend to focus on a few predefined rules and have limited capability for recognizing general circuit topology and applying rules at the full-chip level.

Previous methodologies have been proposed to address chip-level ESD verification [7–12]. These methods are based on the human body model (HBM) and the charged device model (CDM). They either analyze voltage drops along ESD-critical discharging paths between pairs of pads or perform simulations to find voltage clamping for each pad. But again, these methods all employ some pre-defined algorithms and offer limited flexibility for checking different ESD rules for different designs.

Methodology flow

As an alternative, we developed a new full-chip ESD verification methodology, using a specialized verification engine and an ESD-specific rule deck, to address the challenge of providing a generic solution [13]. The Calibre® PERC (Progammable Electrical Rule Checker) solution is not based on modeling or simulation—it literally checks all elements in the entire design for violations. It isn’t limited to a list of pre-defined ESD rules. Instead, Calibre PERC provides a generic framework that allows a designer to specify his or her own rules.

Figure 1 outlines the proposed flow. Verification using this flow needs two inputs: a SPICE netlist and an ESD rule deck. The netlist can be a schematic netlist or a netlist extracted from the layout. In the latter case, the LVS-like run set used for extraction must ensure that all ESD protection devices are extracted, using ESD marking layers if necessary. The netlist must also have the proper text names for pads so that I/O pads and power and ground domains can be established. In general, though, text names in the netlist are not used for verification.

Figure 1. Verification flow using Calibre PERC.

From the input netlist, graph data structures are built first, with one graph for each cell. The verification engine then parses the rule deck and runs a hierarchical algorithm on the graphs to check for ESD violations. Results are written to a report file.

The ESD rule deck specifies the ESD design rules to be checked. Calibre PERC includes a specification language for writing ESD rules. The specification language is a key to making the verification method generic.

Specification language for writing ESD rules

The specification language is embedded within the Tcl general-purpose programming language. In addition to the standard Tcl constructs such as looping and branching, the rule deck provides a set of commands dedicated to writing ESD rules, called ESD commands. Each ESD rule is written as a Tcl procedure.

The ESD commands do not make any assumptions about the structures or contents of the ESD commands being run. They simply provide basic functions that are essential for specifying ESD rules. The ESD commands can be divided into three groups:
  • Initialization commands
  • Rule checking commands, and
  • Reporting commands.

Initialization commands are used to establish I/O pads, as well as power and ground domains, based on pad names. These commands will go through the entire netlist and attach proper attributes, called net types, to the named nets. They can also establish electrical paths and attach path types to all nets in the design. The rule-checking commands are used to do the actual checking. Because ESD rules can cover all kinds of circuit topology, these commands allow a designer to traverse the netlist and access all elements in the design. Rule-checking commands can check types and properties of devices and nets.

The reporting commands are used to annotate the results. Because this is a generic solution, there is no built-in definition of an ESD violation. A designer can add comments to these commands that describe what constitutes a violation.

Examples of ESD rules for verification

Each rule listed here was implemented using the above generic framework and is shown in pseudo code. Rule 1 and Rule 2 are for I/O protection (Figure 2). Rule 3 is for protection of signals crossing power domains (Figure 3).

Rule 1: Primary Protection for I/O Pad

For each net in design,

IF net is connected to IO Pad THEN
 check for up HBM diode and down HBM diode
IF diode(s) missing THEN
 ESD Error

Rule 2: Secondary Protection for I/O Pad

For each net in design,

IF net is connected to input buffer and IO Pad THEN
 check for CDM up diode and CDM down diode
 check if CDM resistor exists and is correct value
IF diode(s) missing or resistor incorrect THEN
 ESD Error

Figure 2. A double diode-based RC-triggered rail clamp ESD protection strategy [15].

Rule 3: Power Domain Crossing

For each net in design,

IF net connects driver and receiver THEN
 check power domains of driver and receiver
IF different power domains THEN
 check for back to back diodes
IF back to back diodes do not exist THEN
 ESD error

Figure 3. An ESD protection design with a resistor-diode clamp [14].

Results from designs in production

This approach was put into practice on a 10-level 90-nm SoC chip with more than 400 million transistors. Although mostly digital, the chip contained significant mixed-signal content including 10 analog-intensive macros. Even with hundreds of millions of nets to check, the ESD-rules verification program was able to verify these three ESD rules in 15.25 minutes.

Any resulting issues could be seen in the results-viewing environment (Figure 4). In addition to displaying designer-defined text and debug messages, we were able to specify hyperlinks to ease the debugging process.

Figure 4. Results from program run showing net 2767 identified by rule_2 as crossing multiple power domains (VSS and VSSIO).

For example, as shown in Figure 2, net 2767 has one receiver (X1/M62) and three drivers (X2/M331, X2/M341, X2/M366). Further investigation of these devices showed that multiple power domains had been traversed (VSS and VSSIO). Selection of the net name 2767 in this environment enabled the drawing of a schematic view of this net (Figure 5), which also identified multiple power domains being traversed.

Figure 5. Schematic showing net 2767 traversing multiple power domains (VSS and VSSIO).

Although Rule 3 was coded specifically to check power domain crossing, this domain checking technique can be used for detection of other “domain-like” problems, such as clock domain crossing.

Because report creation relied heavily on strings and hyperlinks defined by the designer and coded into the ESD rule, these strings and hyperlinks were customized to provide the desired level of debugging detail. With the use of a results viewing environment, this enabled easy access to the actual design elements at fault.

Future needs

The current approach only checks intentionally designed ESD devices. However, parasitic ESD-type devices often compete against intentionally designed ESD devices and can cause early failure.

Also, the current approach only checks the ESD protection scheme at the netlist level. As the ESD design window between the maximum operating voltage and the breakdown voltage gets smaller, parasitic resistances are becoming a major issue for ESD robustness. In the future, consideration of parasitic interconnect resistances will be important.


We were able to demonstrate that this methodology is a viable approach for the automation of ESD rules verification. Its generic framework provides flexibility for detection of the ESD rules being verified. In addition to providing sufficient flexibility to identify and report the ESD structures of interest, Calibre also provided sufficient capacity to deliver runtimes acceptable for verification of large full-chip designs. Coding time for these specific ESD structures within Calibre PERC, including identification and reporting, took less than one day. We anticipate that when a designer is familiar with the specification language, coding of additional checks of similar complexity could take only one to two hours to complete.

By Matthew Hogan

and Ziyang Lu

Matthew Hogan is a Technical Marketing Engineer for Mentor Graphics Corp. in Wilsonville, Oregon. With over 10 years of design and field experience, Matthew is well-versed in the issues that are imposed on today’s aggressive designs. He holds a BEng and an MBA.

Ziyang Lu is a Senior Software Developer at Mentor Graphics, with more than 13 years of experience in electronic design automation and automated test equipment. He holds an MS in Computer Science (Mississippi State University) and a PhD in Applied Mathematics (Tulane University).


1. A. Wang, On-Chip ESD Protection for Integrated Circuits, Kluwer Academic, 2002.
2. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, John Wiley & Sons, 2002.
3. M. Ker, C. Wu, H. Chang, and T. Wu, "Whole Chip ESD Protection Scheme for CMOS Mixed-Mode ICs in Deep-Submicron CMOS Technology," Proceedings of the IEEE Custom Integrated Circuits Conference, 1997, pp. 31–34.
4. S. Sinha, H. Swaminathan, G. Kadamati, and C. Duvvury, "An Automated Tool for Detecting ESD Design Errors," Proceedings of the ESO/ESD Symposium, 1998, pp. 208–217.
5. Q. Li, Y.J. Huh, J.W. Chen, P. Bendix, and S.M. Kang, "ESD Design Rule Checker," IEEE ISCAS, 2001, pp. 499–502.
6. M. Ker and J. Peng, "Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology," Proceedings of the IEEE Custom Integrated Circuits Conference, 1998, pp 537–540.
7. J. Lee, K. Kim, and S. Kang, "VeriCDF: A New Verification Methodology for Charged Device Failures," Proceedings of the 39th Design Automation Conference, 2002, pp. 874–879.
8. H. Qian, J.N. Kozhaya, S.R. Nassif, and S.S. Sapatnekar, "A Chip-level Electrostatic Discharge Simulation Strategy," Proceedings of the IEEE/ACM International Conference Computer Aided Design, 2004, pp. 315–318.
9. M. Baird and R. Ida, "VerifyESD: A Tool for Efficient Circuit Level ESD Simulations of Mixed-Signal ICs," Proceedings of the ESO/ESD Symposium, 2000, pp. 465–469.
10. R. Zhan, H. Xie, H. Feng, and A. Wang, "ESDZapper: A New Layout-level Verification Tool for Finding Critical Discharging Path under ESD Stress," Proceedings of the ASPDAC, 2005, pp. 79–82.
11. S. Hayashi, F. Minami, and M. Yamada, "Full-Chip Analysis Method of ESD Protection Network," Proceedings of the ISQED, 2004, pp. 439–444.
12. H.-Y. Liu, C.-W. Lin, S.-J. Chou, W.-T. Tu, C.-H. Liu, Y.-W. Chang, and S.-Y. Kuo, "Current Path Analysis for Electrostatic Discharge Protection," Proceedings of the ICCAD, 2006, pp. 510–515.
13. T. Pompl, C. Schlunder, M. Hommel, H. Nielen, and J. Schneider, "Practical Aspects of Reliability Analysis for IC Designs," Proceedings of the Design Automation Conference, 2006, pp. 193–198.
14. Shih-Hung Chen, et. al., "Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses," IEEE Transactions On Device And Materials Reliability, Vol. 8, No. 3, September 2008.
15. Industry Council on ESD Target Levels, "White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements," August 2007, Revision 1.0.

Go to the Mentor Graphics Corp. website to learn more.

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