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Verification and Generation of Constraints  
Publication: Design & Reuse
Contributor: Atrenta, Inc.
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August 13, 2009 -- As today's designs become more complex, so too do their constraints. Design functionality typically gets a lot of attention – through code review, functional verification, etc. However, the constraints themselves usually do not get the same level of attention. This is ironic given that the critical implementation and timing analysis steps are dependent on quality constraints.

The complexity of constraints is further increased by the following design characteristics: low-power applications (e.g., handheld devices) require extensive clock gating, and pad limited designs require a high degree of input multiplexing

This article highlights and discusses the importance of constraint validation early in the design flow, and analyzes the impact of this validation approach on a real design. The article then looks at the possibility of generating constraints using automated techniques – and once again, presents the results of trying it on a new design.

By Sanjay Churiwala, Guru S. Shindaghatta, Wei Jiang, and Andrew K. Pua. (Churiwala is Senior Director of Engineering, Atrenta and Shindaghatta is Principal Application Engineer at Atrenta, Inc.; Jiang and Pua are Senior IC Designers at Texas Instruments, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

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Atrenta, Inc.
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Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, assertions, assertion based verification, assertion-based verification, ABV, Design & Reuse, Atrenta,
590/29585 8/13/2009 4470 187


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