September 23, 2009 -- The 40-nm process technology node offers clear benefits over prior nodes, including the 65-nm node and the more recent 45-nm node. One of the most attractive benefits is higher integration. This enables semiconductor manufacturers to pack greater functionality into less physical space at lower costs. Although increased density and performance are valuable benefits, one of the most pressing design considerations for today's system developers is power consumption. The need for low power consumption is being driven today by the trends toward compactness of form factor, portability, and power efficiency.
In addition to the silicon processing techniques, reducing power consumption requires architectural innovations. Smaller geometries provide the added benefit of reduced dynamic power consumption by way of less parasitic capacitances, as well as raise static power unacceptably due to increased leakage currents if no steps are taken to reduce it. While intelligent systems are designed to minimize dynamic power—for example, powering down certain sections of an unused chip or unused logic—the focus of this article is to explore some architectural innovations used to minimize the constant drain of power consumption (also known as static power). Static power is like the annoying leaky water faucet in the house that keeps you awake at night when you are trying to sleep.
How do FPGA designers minimize static power at smaller process geometries without affecting chip performance? To answer this question, let's first examine the basics of power and then look at how static power can be minimized.
By Seyi Verma. (Verma is a senior member of the high-end technical analysis staff at Altera Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.
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