Through-silicon vias (TSVs) are not exactly new. In fact, some mobile phones in Japan already contain TSVs, and there are also military and medical applications in commercial production. However, until 45nm, interest in TSVs was less common. But, with advances in 32/28- and 22-nm technology somewhat slowed by technological issues, TSVs are beginning to emerge as a viable construct that will enable the industry to continue expanding the functionality of chips at 45nm and below.

So what exactly is a TSV, and why is it becoming a practical technology now? To answer that question, let’s take a quick look at chip-stacking technologies.

Chip stacking construction (See Figure 1.) is used for a variety of reasons, chief among them:

It allows for the efficient mixing of multiple process technologies. It improves system reliability and robustness by creating an internal stack, reducing the need for "chipsets" on the printed circuit board. It provides dense packaging.

Figure 1. The "stacked chip" concept.

Regardless of the interconnect technology used, stacked chips allow for the mixing of different process nodes and manufacturing technologies within the same integrated circuit (IC) package. Often these are referred to as system-in-package (SiP) designs.

The most prevalent technique for connecting stacked chips is wire bonding, where a wire is routed from the die down to the chip package and back up, as illustrated in Figure 2. The benefit of wire bond technology is that it’s relatively inexpensive, well-characterized and has been used for quite some time. Because of this, there is significant industry experience with wire-bond packaging. However, because you can only place wire bonds on the outside edges of chips, you’re limited as to how many connections you can make, and the distance these wires have to run can be significant in electrical terms. That distance changes the timing, which creates additional electrical issues that must be resolved.

Figure 2. Stacked chips with wire bonding.

Flip-chip construction has also been used to connect two chips by "flipping" one chip over, as shown in Figure 3. Using flip-chip technology lets designers place two chips together in close proximity. The downside is that only one chip can be flipped.

Figure 3. Flip-chips allow two dies to be connected without the use of wire bonding.

TSVs are used to make a direct connection through multiple stacked chips. A design that contains TSVs typically is very similar to a regular IC design, except that it contains through-hole conductivity paths (vias) through the actual substrate. The advantage of TSVs over wire-bonding is the ability to route the connection through the chip, rather than being constrained to the perimeter. Likewise, the advantage of TSVs over flip-chip construction is the ability to stack more than two die in a configuration. Figure 4 illustrates a TSV construction.

Figure 4. TSVs allow multiple dies to be stacked.

Bonding techniques

While copper currently seems to be the most popular material for the TSV, tungsten has also been used. Devices and "regular" metal layers are manufactured on the front side of the chip, as they normally would be, and a limited number (typically 0 to 2) of metallization layers are on the back. While the front metal and devices are manufactured to typical 45-nm or 32/28-nm dimensions, the metal routing on the back side is typically of significantly larger dimensions.

Microballs of solder (sometimes called "micro bumps") are typically used to connect one chip to another. The microball position on the back of the chip can be in precisely the correct location (in which case a microball directly on the TSV is sufficient), or offset, in which case some sort of back metal routing is required to provide an electrical connection between the TSV and the microball. Employing microballs has the advantage of compensating for any planar issues that may exist between the mating faces of the two die. In addition, the distance from one routing layer to another (chip-to-chip) is considered too large to be concerned about coupling from one chip to another.

Other bonding techniques do exist, including:

Direct oxide bonding. Metal to metal bonding. Adhesive bonding (in conjunction with Cu-Cu bonding).

If these bonding alternatives, which place both chips in very close proximity to each other, come into widespread use, across-chip parasitic verification may need to be investigated and modeled.

A convergence of disciplines

TSV designs represent a convergence of two previously different disciplines: system-on-chip (SOC), and system-in-package (SiP). With the ability to stack chips on top of each other in 3D space, designers are now able to utilize dies not only of different process nodes, but also of different manufacturing types (SiGe, SOI, CMOS Low voltage, CMOS High voltage, BiPolar, GaAs, etc.). The ability to mix and match these different dies into a single system also allows designers to focus on their core design strengths, and utilize "commodity" parts (such as memory or an RF transmitter) as part of a TSV design.

Utilizing stacked chips in memory-intensive designs, such as NAND flash, CPUs, or any design that incorporates memory, is an effective design solution. Going "up" allows the designer to stay at today's "reasonable" (45/32/28 nm) process nodes and derive the benefit of a volume manufacturing process, rather than having to move to the next process node. Designers who have an existing design to which they want to add memory, or for which they want to increase the logic on the base die, can put additional memory onto a TSV die, and go "up." A design could have memory at 32/28nm connected to a main chip at 45nm. Depending on the design, engineers can factor in the loading of additional TSV memory dies on top, and easily create multiple product variations with 1-, 2-, 3-, or 4-Gbit product version of the design by simply adding additional TSV dies on top.

Designs at advanced process nodes, such as 45nm, may consider a move to 32/28nm. TSV adoption enables the continued use of 45 and 32/28nm by reducing the need to use smaller process nodes while maintaining Moore’s Law. Using TSV technology allows companies to mix and match existing process nodes to maximize chip functionality without having to advance to the next production node.

A marriage of incompatibles

Another use of TSV technology is connecting two chips that were not originally designed to work together. A TSV "interposer" (a passive TSV chip that provides for pin re-mapping from one chip to another) allows for combinations of existing chips that would be otherwise incompatible, as shown in Figure 5.

Figure 5. Using a TSV interposer allows for signal re-mapping from one chip to another.

In the design realm, there is still some disagreement over whether it is better to design TSV chip stacks as individual chips, or to design the 3D stack all together. There is some traction for the individual chip design approach, because that is how the die will be manufactured. Designers will need to verify interfaces between die and make sure they all line up.

From a manufacturing perspective, the industry is still struggling with the question of how to produce TSV chips and how to get acceptable yields. There are a couple of key manufacturing concerns:

How do you manufacture a die stack that’s 3-5 high, and make sure that all of the chips are known good dies? How do you account for thermal considerations? Since chips are intimately stacked, more heat is generated, with less area over which to dissipate. Some proposals in this area recommend a dedicated micro-fluidic cooling system.

The widespread adoption of TSV technology could also lead to the development of commodity TSV chips. The 3D-IC Alliance has proposed the IMIS (intimate memory interface specification) standard to specify the location of each microball and what signal should be at each location. If this standard is adopted for TSV memory designs, design houses would have the flexibility to source those standardized memories in their design.

Presently, there is much interest in solving TSV design and production issues. TSVs provide superior scalability over the tried and true wire-bond methods, allowing for greater flexibility in design configurations. This flexibility in the design space presents an opportunity to deliver products with enhanced capabilities without moving to smaller production nodes.

By Matthew Hogan.

Matthew Hogan is a Caliber marketing engineer for Mentor Graphics. With over 15 years of design and field experience, he is well-versed in the issues that are imposed on today's aggressive designs. Matthew is an IEEE senior member and ACM member.