July 24, 2003 -- Designers today continue to be challenged with the need to manage power, timing and signal integrity concurrently throughout the design flow. Traditional power optimization techniques and today's power-aware design flows are proving insufficient in the design of systems-on-a-chip (SoCs) for next-generation applications, and must evolve to enable design for energy efficiency. This tutorial focuses on the need for design flows that enable energy efficient design through existing and emerging techniques, such as dynamic and adaptive voltage and frequency scaling.

By David Tamura, Barry Pangrle, and Rajiv Maheshwary. (Tamura is the Design Technology Manager for National Semiconductor's Technology and Infrastructure Group; Pangrle is the Senior R&D Manager for ASIC Power Products at Synopsys; and Maheshwary is the director of marketing for Static Timing and Power products at Synopsys.)