October 19, 2009 -- Historically, the speed and complexity of electronic circuits required for manufacturing has out-matched the interconnects used to join circuits together. A first approximation of interconnect performance controls are: power consumption (capacitance, voltage, frequency), signal speed (resistance, inductance, capacitance), and sSignal integrity (inductance, capacitance).

Various strategies have been devised to address these controls. For example, materials and process innovations have lead to copper tracks and low-k dielectrics, while novel circuit designs have given rise to the 64-bit-wide bus, multi-data transfers per clock cycle, and synchronous clock technologies.

However, the performance of each interconnect is fundamentally dictated by its length, width, and thickness. Device integration solutions like system-on-chip (SOC) and 3D-stacking are intended to directly address these controls. In the case of 3D-stacking, the objective is to replace the long, horizontal, wiring traces that become necessary when die are placed side-by-side with short, vertical pathways, concomitantly reducing the three fundamental controls of resistance, inductance, and capacitance.

Making vertical interconnects generally requires some form of through-silicon via (TSV) technology. TSVs are conceptually very simple to produce and many variations exist. A common implementation is a hollow pipe with near-vertical sidewalls, machined through the thickness of the silicon. A dielectric film overlaid with conductive metal is applied to the sidewalls of the pipe. Generally, TSVs furnish electrical pathways between bond pads on one face of the die and lands on the opposing face.

By Gilles Humpston, Bents Kidron and Moshe Kriman. (Humpston, director of research and development at Tessera Technologies, Inc., Kidron is Vice President of Marketing, Wafer-level Packaging, and Kriman is Senior Director of Engineering.)