November 16, 2009 -- Aldec Corp. has announced a low-cost Linux RTL simulator. The new configuration supports both Linux and Windows mixed-language VHDL/ Verilog simulation. Riviera-PRO LV is a multi-platform RTL and gate-level simulator that supports IEEE VHDL, Verilog and SystemVerilog (Design) IEEE standard, Xilinx SecureIP and VHDL/ Verilog IP encryption. The new configuration has no limitations on ASIC or FPGA device support and includes an advanced waveform toolset and fast debugging.

Availability