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Publication: EE Times Programmable Logic Designline
Contributor: Actel Corp.
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October 28, 2009 -- The last decade has seen rapid and permanent change in technology markets towards smaller, more portable systems. Many large systems that once sat on a desktop are now portable, while portable devices that used to fit in a backpack or briefcase must now fit in a shirt pocket. This has brought many additional design demands, most obviously battery life. Time between recharging - once measured in hours " must now stretch for days.

Size and power considerations are now often the top priority in many system designs, but portability and long-lasting power can become conflicting design requirements. Design teams are continually challenged with packing more and more functionality into smaller and smaller packages, and then somehow squeezing enough power into the same package to keep everything running for days, weeks or even months at a time on a single battery charge.

Meeting size and power requirements in portable devices typically requires ASICs. Increased market pressures comprising shortened development cycles and lower cost, however, make the time and expense required for ASIC development a high design risk. Taking time to design and debug an ASIC could lead to missing ever shrinking market windows or drive development costs very high that making a profit is impossible.

By Wendy Lockhart. (Lockhart is a Principal Engineer with Actel Corp.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times Programmable Logic Designline website.

Read more about
Actel Corp.

Keywords: FPGAs, field programmable gate arrays, FPGA design, power analysis, power optimization, low power design, low-power design, EE Times Programmable Logic Designline, Actel,
590/30174 10/30/2009 5178 364
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