January 4, 2010 -- The significant burden of parasitics on the performance of post-layout verification forces design engineers to use additional techniques in order to match the requirements of next-generation designs. A real gap appears between layout extraction and circuit simulation when adding layout parasitics into the flow. A review of the existing techniques as well as a merciless way to doubtlessly validate netlist reduction and circuit extraction are presented in this paper.
By Mathias Silvant. (Silvant is President and CEO of edXact SA.)
This brief introduction has been excerpted from the original copyrighted article.
