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Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies  
Company: Synopsys, Inc.
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The physical layer is responsible for the transmission of the raw bit stream over the PHYsical transport medium and is the lowest layer within the OSI network model. With high-speed interfaces such as the serial protocols USB 2.0, PCI Express®, SATA, and DDR2, the PHY provides the bridge between the digital and modulated parts of the interface. The trend is to integrate these mixed-signal interfaces into SoC’s that are manufactured in digital logic deep sub-micron technologies with channel lengths of 65nm and 45nm.

By Navraj S. Nandra, Director of Marketing Mixed-Signal IP, Synopsys Inc.

Access the entire document on the Synopsys, Inc. website.

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Keywords: ASICs, ASIC design, mixed signal design, mixed-signal design, DesignWare IP, intellectual property, cores, Synopsys,
205/30495 1/20/2010 2059 115
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