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Reusable VHDL IP In the Real World  
Publication: Design & Reuse
Contributor: RF Engines, Ltd.
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February 18, 2010 -- Reuse has been an industry buzzword for years now. It is hardly a new idea, and probably goes back as far as the time when man first realised he could use the same fire both for keeping warm and for roasting his sabre-tooth tiger ribs. When it comes to IP, reuse can be an extremely powerful way of saving resources and shortening project timescales.

At RF Engines, we find that reusing existing IP is very desirable. Not only does it save us development time and help us fulfil challenging delivery requirements, but making use of pre-proven components also helps give customers confidence in our designs.

Another dimension to this is that multi-FPGA designs are becoming increasingly widespread, and there are obvious advantages to having a chip-level infrastructure that is reusable within the project.

Reuse, then, is clearly "A Good Thing." However, in practice it has often proven surprisingly difficult to achieve. So it is worth bearing in mind a few principles and techniques that can be applied to make it more straightforward. Though it would be foolish to say that creating reusable VHDL doesn't require any extra effort, it frequently pays significant dividends in the longer term.

By Matt Bridle. (Bridle is with RF Engines, Ltd.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

Read more about
RF Engines, Ltd.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, VHDL,
596/30752 2/18/2010 2946 277
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