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Chip Synthesis: A New Approach to RTL Implementation  
Publication: EE Times EDA Designline
Contributor: Oasys Design Systems
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February 16, 2010 -- Traditional synthesis is coming apart at the seams, especially for designs larger than 20 million gates. Since it relies on gate-level optimization, traditional synthesis is very limited in the size of block that it can handle and so the designer is forced to divide the design into a large number of smaller blocks. However, since place and route can handle much more than these smaller blocks, the synthesized blocks are aggregated back together to bigger blocks. But managing timing and constraints through this process of stitching the blocks together again is very painful, hence almost literally traditional synthesis comes apart at the seams.

By Paul van Besouw. (van Besouw is President and CEO, Oasys Design Systems.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Oasys Design Systems
on SOCcentral.com

Keywords: ASICs, ASIC design, ASIC synthesis, EDA, EDA tools, electronic design automation, EE Times EDA Designline, Oasys Design Systems,
596/30812 2/16/2010 2722 184


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